參數(shù)資料
型號(hào)： P83C562EFA
廠商： NXP Semiconductors N.V.
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁(yè)數(shù)： 18/52頁(yè)
文件大小： 299K
代理商： P83C562EFA
1997 Apr 08
18
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
12 TIMER/ COUNTERS
The P8xC562 contains:
Three 16-bit timer/event counters: Timer 0, Timer 1 and
Timer 2
One 8-bit Watchdog Timer.
12.1
Timer 0 and Timer 1
Timer 0 and Timer 1 may be programmed to carry out the
following operations:
Measure time intervals and pulse durations
Count events
Generate interrupt requests.
Timer 0 and Timer 1 can also be programmed
independently to operate in three modes:
Mode 0 8-bit timer or 8-bit counter each with
divide-by-32 prescaler
Mode 1 16-bit time-interval or event counter
Mode 2 8-bit time-interval or event counter with automatic
reload upon overflow.
Timer 0 can be programmed to operate in an additional
mode as follows:
Mode 3 one 8-bit time-interval or event counter and one
8-bit time-interval counter.
When Timer 0 is in Mode 3, Timer 1 can be programmed
to operate in Modes 0, 1 or 2 but cannot set an interrupt
request flag or generate an interrupt. However, the
overflow from Timer 1 can be used to pulse the serial port
transmission-rate generator.
The frequency handling range of these counters with a
16 MHz crystal is as follows:
In the timer function, the timer is incremented at a
frequency of 1.33 MHz; a division by 12 of the oscillator
frequency
0 Hz to an upper limit of 0.66 MHz when programmed
for external inputs.
Both internal and external inputs can be gated to the
counter by a second external source for directly measuring
pulse durations.
The counters are started and stopped under software
control. Each one sets its interrupt request flag when it
overflows from all logic 1s to all logic 0s (or automatic
reload value), with the exception of Mode 3 as previously
described.
12.2
Timer T2 Capture and Compare Logic
Timer T2 is a 16-bit timer/counter which has, coupled to it,
capture and compare facilities. The operational diagram is
shown in Fig.10.
The 16-bit timer/counter is clocked via a prescaler with a
programmable division factor of 1, 2, 4 or 8. The input of
the prescaler is clocked with
1
12
of the oscillator
frequency, or with positive edges on the T2 input, or it is
switched to the off position. The prescaler is cleared if its
division factor or its input source is changed, or if the
timer/counter is reset. T2 is readable on-the-fly, but
possesses no extra read latches; this means that software
precautions have to be taken against misinterpretation on
overflow from least to most significant byte during a read.
T2 is not loadable and is reset by the RST signal or at the
positive edge of the input signal RT2, if enabled. In the Idle
mode the timer/counter and prescaler are reset and
halted.
T2 is connected to four 16-bit Capture Registers: CT0,
CT1, CT2 and CT3. These registers are loaded with the
contents of T2 and an interrupt is requested upon receipt
of the input signals CT0I, CT1I, CT2I or CT3I. These input
signals are shared with Port 1. Using the Capture Register
(CTCON), these inputs may invoke capture and interrupt
request on a positive or negative edge or on both edges.
If neither a positive nor a negative edge is selected for a
capture input, no capture or interrupt request can be
generated by this input.
The contents of the Compare Registers CM0, CM1 and
CM2 are continually compared with the counter value of
Timer 2. When a match is found an interrupt may be
invoked. Using the match signal of CM0, the controller sets
bits 0 to 5 of Port 4, if the corresponding bits of the Set
Enable Register are logic 1s.
Considering a match with CM1, if the corresponding bits of
the Reset/toggle Enable Register (RTE) are logic 1, then
the controller will use the match signal to reset bits 0 to 5
of Port 4. Bits 6 and 7 of Port 4 may be toggled by the
signal that indicates a match of Timer T2 and CM2 if the
corresponding bits of RTE are logic 1. CM0, CM1 and CM2
are reset by the RST signal.
Port 4 can be read and written by software without
affecting the toggle, set and reset signals. At byte overflow
of the least significant byte, or at a 16-bit overflow of the
timer/counter, an interrupt sharing the same interrupt
vector is requested. Either one or both of these overflows
can be programmed to request an interrupt.
All interrupt flags must be reset by software.
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