參數(shù)資料
型號(hào)： P83C557E6
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 8-bit microcontroller
中文描述： 單芯片8位微控制器
文件頁(yè)數(shù)： 65/72頁(yè)
文件大?。?/td> 374K
代理商： P83C557E6
Philips Semiconductors
Product specification
P83C557E4/P80C557E4/P89C557E4
Single-chip 8-bit microcontroller
1999 Mar 02
65
11.
AC CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
V
DD
= 5 V
±
10% (EBx), V
SS
= 0 V, t
CLK
min = 1/fmax (maximum operating frequency)
V
DD
= 5 V
±
10% (EFx), V
SS
= 0 V, t
CLK
min = 1/fmax (maximum operating frequency)
T
amb
= 0
°
C to +70
°
C, t
CLK
min = 63 ns for P8xC557E4EBx
T
amb
= –40
°
C to +85
°
C, t
CLK
min = 63 ns for P8xC557E4EFx
C1 = 100 pF for Port 0, ALE and PSEN ; C1 = 80 pF for all other outputs unless otherwise specified.
12MHz CLOCK
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1/t
CLK
t
LHLL
t
AVLL
t
LLAX
60
System clock frequency
3.5
16
MHz
60
ALE pulse width
127
85
2t
CLK
–40
t
CLK
–40
t
CLK
–30
ns
60
Address valid to ALE LOW
43
23
ns
60
Address hold after ALE LOW
53
33
ns
t
LLIV
t
LLPL
t
PLPH
t
PLIV
60
ALE LOW to valid instruction in
234
150
4t
CLK
–100
ns
60
ALE LOW to PSEN LOW
53
33
t
CLK
–30
3t
CLK
–45
ns
60
PSEN pulse width
205
143
ns
60
PSEN LOW to valid instruction in
145
83
3t
CLK
–105
ns
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
60
Input instruction hold after PSEN
0
0
0
ns
60
Input instruction float after PSEN
59
38
t
CLK
–25
5t
CLK
–105
10
ns
60
Address to valid instruction in
312
208
ns
60
PSEN LOW to address float
10
10
ns
Data Memory
t
AVLL
t
LLAX
t
RLRH
t
WLWH
61, 62
Address valid to ALE LOW
43
23
t
CLK
–40
t
CLK
–35
6t
CLK
–100
6t
CLK
–100
ns
61, 62
Address hold after ALE LOW
48
28
ns
61
RD pulse width
400
275
ns
62
WR pulse width
400
275
ns
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
61
RD LOW to valid data in
252
148
5t
CLK
–165
ns
61
Data hold after RD
0
0
0
ns
61
Data float after RD
97
55
2t
CLK
–70
8t
CLK
–150
9t
CLK
–165
ns
61
ALE LOW to valid data in
517
350
ns
61
Address to valid data in
585
398
ns
t
LLWL
t
AVWL
t
QVWX
t
QVWH
61, 62
ALE LOW to RD or WR LOW
200
300
138
238
3t
CLK
–50
4t
CLK
–130
t
CLK
–50
7t
CLK
–150
3t
CLK
+50
ns
61, 62
Address valid to WR LOW or RD LOW
203
120
ns
62
Data valid to WR transition
33
13
ns
62
Data before WR
433
288
ns
t
WHQX
t
RLAZ
t
WHLH
UART Timing – Shift Register Mode
(Test Conditions: T
amb
= 0
°
C to +70
°
C; V
SS
= 0 V; Load Capacitance = 80pF)
t
XLXL
64
Serial port clock cycle time
62
Data hold after WR
33
13
t
CLK
–50
ns
61
RD low to address float
0
0
0
ns
61, 62
RD or WR HIGH to ALE HIGH
43
123
23
103
t
CLK
–40
t
CLK
+40
ns
1.0
0.75
12t
CLK
μ
s
t
QVXH
t
XHQX
t
XHDX
t
XHDV
64
Output data setup to clock rising edge
700
492
10t
CLK
–133
2t
CLK
–117
0
ns
64
Output data hold after clock rising edge
50
8
ns
64
Input data hold after clock rising edge
0
0
ns
64
Clock rising edge to input data valid
700
492
10t
CLK
–133
ns
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