參數(shù)資料
型號(hào)： P83C557E6
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 8-bit microcontroller
中文描述： 單芯片8位微控制器
文件頁數(shù)： 27/72頁
文件大小： 374K
代理商： P83C557E6
Philips Semiconductors
Product specification
P83C557E4/P80C557E4/P89C557E4
Single-chip 8-bit microcontroller
1999 Mar 02
27
Figure 25. Set enable register (STE).
7
6
5
4
3
2
1
0
STE (EEH)
TG47
TG46
SP45
SP44
SP43
SP42
SP41
SP40
Table 20.
Description of STE bits
SYMBOL
BIT
FUNCTION
TG47
STE.7
If “1” then P4.7 is reset on the next toggle, if LOW P4.7 is set on the next toggle
TG46
STE.6
If “1” then P4.6 is reset on the next toggle, if LOW P4.6 is set on the next toggle
SP45
STE.5
If “1” then P4.5 is set on a match between CM0 and Timer T2
SP44
STE.4
If “1” then P4.4 is set on a match between CM0 and Timer T2
SP43
STE.3
If “1” then P4.3 is set on a match between CM0 and Timer T2
SP42
STE.2
If “1” then P4.2 is set on a match between CM0 and Timer T2
SP41
STE.1
If “1” then P4.1 is set on a match between CM0 and Timer T2
SP40
STE.0
If “1” then P4.0 is set on a match between CM0 and Timer T2
Figure 26. Reset/Toggle enable register (RTE).
7
6
5
4
3
2
1
0
RTE (EFH)
TP47
TP46
RP45
RP44
RP43
RP42
RP41
RP40
Table 21.
Description of RTE bits
SYMBOL
BIT
FUNCTION
TP47
RTE.7
If “1” then P4.7 toggles on a match between CM2 and Timer T2
TP46
RTE.6
If “1” then P4.6 toggles on a match between CM2 and Timer T2
RP45
RTE.5
If “1” then P4.5 toggles on a match between CM1 and Timer T2
RP44
RTE.4
If “1” then P4.4 toggles on a match between CM1 and Timer T2
RP43
RTE.3
If “1” then P4.3 toggles on a match between CM1 and Timer T2
RP42
RTE.2
If “1” then P4.2 toggles on a match between CM1 and Timer T2
RP41
RTE.1
If “1” then P4.1 toggles on a match between CM1 and Timer T2
RP40
RTE.0
If “1” then P4.0 toggles on a match between CM1 and Timer T2
For more information concerning the TM2CON, CTCON, TM2IR and
the STE/RTE registers see IC20 handbook, chapter “80C51 family
hardware description”.
Port 4 can be read and written by software without affecting the
toggle, set and reset signals. At a byte overflow of the least
significant byte, or at a 16-bit overflow of the timer/counter, an
interrupt sharing the same interrupt vector is requested. Either one
or both of these overflows can be programmed to request an
interrupt.
All interrupt flags must be reset by software.
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