參數(shù)資料
型號(hào)： P83C552IFB
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 8-bit microcontroller
中文描述： 單芯片8位微控制器
文件頁(yè)數(shù)： 11/23頁(yè)
文件大小： 185K
代理商： P83C552IFB
Philips Semiconductors
Product data
80C552/83C552
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
2002 Sep 03
11
DC ELECTRICAL CHARACTERISTICS
(Continued)
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Analog Inputs
AI
DD
Analog supply current: operating: (16 MHz)
Analog supply current: operating: (24 MHz)
Port 5 = 0 to AV
DD
Port 5 = 0 to AV
DD
1.2
1.0
mA
mA
AI
ID
Idle mode:
P83(0)C552EBx
P83(0)C552EFx
P83(0)C552EHx
P83(0)C552IBx
P83(0)C552IFx
50
50
100
50
50
μ
A
μ
A
μ
A
μ
A
μ
A
AI
PD
Power-down mode:
2 V < AV
< AV
DD
max
P83(0)C552xBx
P83(0)C552xFx
P83(0)C552xHx
50
50
100
μ
A
μ
A
μ
A
AV
IN
AV
REF
Analog input voltage
AV
SS
–0.2
AV
DD
+0.2
V
Reference voltage:
AV
REF–
AV
REF+
Resistance between AV
REF+
and AV
REF–
Analog input capacitance
AV
SS
–0.2
V
V
AV
DD
+0.2
50
R
REF
C
IA
t
ADS
t
ADC
DL
e
IL
e
OS
e
G
e
A
e
M
CTC
C
t
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 10 through 15 for I
DD
test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 10 ns; V
IL
= V
SS
+ 0.5 V;
V
= V
– 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = V
; STADC = V
.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 10 ns; V
IL
= V
SS
+ 0.5 V;
V
= V
– 0.5 V; XTAL2 not connected; Port 0 = EW = V
; EA = RST = STADC = V
.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V
DD
;
EA = RST = STADC = XTAL1 = V
SS
.
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
2
C specification, so an input voltage below 1.5 V will be recognized as a
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V
IN
is approximately 2 V.
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9 V
DD
specification when the
address bits are stabilizing.
9. The following condition must not be exceeded: V
DD
– 0.2 V < AV
DD
< V
DD
+ 0.2 V.
10.Conditions: AV
REF–
= 0 V; AV
DD
= 5.0 V, AV
REF+
(80C552, 83C552) = 5.12 V. ADC is monotonic with no missing codes. Measurement by
continuous conversion of AV
IN
= –20 mV to 5.12 V in steps of 0.5 mV.
11. The differential non-linearity (DL
) is the difference between the actual step width and the ideal step width. (See Figure 1.)
12.The ADC is monotonic; there are no missing codes.
13.The integral non-linearity (IL
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset error. (See Figure 1.)
10
k
15
pF
Sampling time
8t
CY
50t
CY
±
1
±
2
±
2
±
0.4
±
3
±
1
μ
s
μ
s
Conversion time (including sampling time)
Differential non-linearity
10, 11, 12
Integral non-linearity
10, 13
Offset error
10, 14
Gain error
10, 15
Absolute voltage error
10, 16
LSB
LSB
LSB
%
LSB
Channel to channel matching
Crosstalk
between inputs of port 5
17
LSB
0–100kHz
–60
dB
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