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參數(shù)資料
| 型號(hào)： | P83C180 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件頁(yè)數(shù)： | 60/84頁(yè) |
| 文件大?。?/td> | 420K |
| 代理商： | P83C180 |
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1997 Dec 12
60
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
19.2.5.3
Parameter Hpol
The mode change interrupt will be issued after 36 to 40
periods of the HSYNC when the polarity is changed from
negative to positive. The polarity indicator Hpol will be
changed from a logic 1 to a logic 0. The mode change
interrupt will be issued after the 60 periods of the HSYNC
when the polarity is changed from positive to negative. The
Hpol will be changed from a logic 0 to a logic 1. A logic 0
represents a positive polarity and a logic 1 represents a
negative polarity.
19.2.5.4
Parameter Hcha
If Hcha is set to HIGH indicating that the period time has
changed for a long period, the Hper and Hpres will be
updated. If the measured period time has become stable
then the two counters will start to count down and the
HENA signal is set to LOW again, thereby disabling the
register Hper and the SR flip-flop for Hpres parameter.
Fig.29 Horizontal mode detection.
handbook, full pagewidth
MGG038
D-FF
SR-FF
D
E
Q
Q
Hper and Hpol
DECISION
CIRCUIT
DIV 16
Hpol
FOSH
FOSH
HENA
Hcnt
Hcha
FOSH
HSYNC
HSYNC_P
Hres
S
R
Hpres
Hper
Q
Hhgh
Hlow
12-BIT
COUNTER
R
Q 11 to Q0
FOSH
12-BIT
REGISTER
Q11 to Q0
Hper
CHANGE
DETECTOR
MODE
CHANGE
STABILIZATION
AND
COMPARISON
CIRCUIT
D11 to D0
E
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