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參數(shù)資料
| 型號(hào)： | P83C180 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件頁數(shù)： | 45/84頁 |
| 文件大?。?/td> | 420K |
| 代理商： | P83C180 |
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1997 Dec 12
45
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
17.2
Host type detection
The detection procedure conforms to the sequences
proposed by “VESA Monitor Display Data Channel (DDC)
specification” The monitor needs to determine the type of
host system:
DDC1 or OLD type host
DDC2B host (host is master, monitor is always slave)
DDC2B+/DDC2AB (ACCESS.bus) host.
The sequence of detection is described in the flow chart
illustrated in Fig.24.
The monitor where P83C880 resides is always both DDC1
and DDC2 compatible with DDC2 having the higher
priority. The display (i.e. P83C880) shall start transmitting
DDC1 signals whenever it is switched on and VSYNC is
applied to it from the host for the first time. The display
shall switch to DDC2 within 3 system clocks as soon as it
sees a HIGH-to-LOW transition on the clock line (SCL),
indicating that there are both DDC2 devices connected to
the bus. Under that condition, the Mode flag M0 will be
changed from the default setting logic 0 to logic 1.
Accordingly, the interrupt will be invoked by setting flag
SWH_int (DDCCON.1) as HIGH (this flag must be cleared
by the interrupt service routine). This procedure will cause
a transmission error. However, both the display and the
host shall have error detection and a method to recover
from the temporary transmission errors.
Figure 24 illustrates the concept and interaction between
the monitor and the host. After power-on, the DDC1enable
bit (DDCCON.2) is set by software, setting the monitor as
a DDC1 device. Therefore, the Mode flag M0, is set as
logic 0. Following VSYNC as clock, the monitor (i.e.
P83C880) will transmit EDID data stream to the host.
However, if DDC2 clock (SCL clock) is present, the
monitor will be switched to DDC2B device with the Mode
flags setting as logic 1. Software will determine whether it
is a DDC2B, DDC2B+, or DDC2AB protocol.
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