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參數(shù)資料
| 型號(hào)： | P8242AH |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER |
| 中文描述： | 8-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 243K |
| 代理商： | P8242AH |
UPI-41AH/42AH
A.C. CHARACTERISTICSDPROGRAMMING
T
A
e
25
§
C
g
5
§
C, V
CC
e
6V
g
0.25V, V
DDL
e a
5V
g
0.25V, V
DDH
e
12.5V
g
0.5V
(8741AH/8742AH ONLY)
Symbol
Parameter
Min
Max
Units
t
AW
Address Setup Time to RESET
u
Address Hold Time After RESET
u
Data in Setup Time to PROG
v
Data in Hold Time After PROG
u
4t
CY
t
WA
4t
CY
t
DW
4t
CY
t
WD
4t
CY
t
PW
Initial Program Pulse Width
0.95
1.05
ms
(1)
t
TW
Test 0 Setup Time for Program Mode
4t
CY
t
WT
Test 0 Hold Time After Program Mode
4t
CY
t
DO
Test 0 to Data Out Delay
4t
CY
t
WW
RESET Pulse Width to Latch Address
4t
CY
t
r
, t
f
PROG Rise and Fall Times
0.5
100
m
s
t
CY
CPU Operation Cycle Time
RESET Setup Time Before EA
u
2.5
3.75
m
s
t
RE
4t
CY
t
OPW
Overprogram Pulse Width
2.85
78.75
ms
(2)
t
DE
EA High to V
DD
High
1t
CY
NOTES:
1. Typical Initial Program Pulse width tolerance
e
1 ms
g
5%.
2. This variation is a function of the iteration counter value, X.
3. If TEST 0 is high, t
DO
can be triggered by RESET
.
A.C. CHARACTERISTICS
PORT 2
T
A
e
0
§
C to
a
70
§
C, V
CC
e a
5V
g
10%
Symbol
Parameter
f(t
CY
)
(3)
1/15 t
CY
b
28
Min
Max
Units
t
CP
Port Control Setup Before Falling Edge of PROG
55
ns
(1)
t
PC
Port Control Hold After Falling Edge of PROG
1/10 t
CY
8/15 t
CY
b
16
125
ns
(2)
t
PR
PROG to Time P2 Input Must Be Valid
650
ns
(1)
t
PF
Input Data Hold Time
0
150
ns
(2)
t
DP
Output Data Setup Time
2/10 t
CY
1/10 t
CY
b
80
250
ns
(1)
t
PD
Output Data Hold Time
45
ns
(2)
t
PP
PROG Pulse Width
6/10 t
CY
750
ns
NOTES:
1. C
L
e
80 pF.
2. C
L
e
20 pF.
3. t
CY
e
1.25
m
s.
14
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