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參數(shù)資料
| 型號： | P8242AH |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER |
| 中文描述： | 8-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 243K |
| 代理商： | P8242AH |
November 1994
Order Number: 210393-008
UPI-41AH/42AH
UNIVERSAL PERIPHERAL INTERFACE
8-BIT SLAVE MICROCONTROLLER
Y
UPI-41: 6 MHz; UPI-42: 12.5 MHz
Y
Pin, Software and Architecturally
Compatible with all UPI-41 and UPI-42
Products
Y
8-Bit CPU plus ROM/OTP EPROM, RAM,
I/O, Timer/Counter and Clock in a
Single Package
Y
2048 x 8 ROM/OTP, 256 x 8 RAM on
UPI-42, 1024 x 8 ROM/OTP, 128 x 8
RAM on UPI-41, 8-Bit Timer/Counter, 18
Programmable I/O Pins
Y
One 8-Bit Status and Two Data
Registers for Asynchronous Slave-to-
Master Interface
Y
DMA, Interrupt, or Polled Operation
Supported
Y
Fully Compatible with all Intel and Most
Other Microprocessor Families
Y
Interchangeable ROM and OTP EPROM
Versions
Y
Expandable I/O
Y
Sync Mode Available
Y
Over 90 Instructions: 70% Single Byte
Y
Available in EXPRESS
D Standard Temperature Range
Y
inteligent Programming Algorithm
D Fast OTP Programming
Y
Available in 40-Lead Plastic and 44-
Lead Plastic Leaded Chip Carrier
Packages
(See Packaging Spec., Order
Y
240800-001)
Package Type P and N
The Intel UPI-41AH and UPI-42AH are general-purpose Universal Peripheral Interfaces that allow the designer
to develop customized solutions for peripheral device control.
They are essentially ‘‘slave’’ microcontrollers, or microcontrollers with a slave interface included on the chip.
Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS
Modules and iAPX family, as well as other 8-, 16-, and 32-bit systems.
To allow full user flexibility, the program memory is available in ROM and One-Time Programmable EPROM
(OTP). All UPI-41AH and UPI-42AH devices are fully pin compatible for easy transition from prototype to
production level designs.
210393–2
Figure 1. DIP Pin Configuration
210393–3
Figure 2. PLCC Pin Configuration
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