參數(shù)資料
型號(hào): P80CE558
廠商: NXP Semiconductors N.V.
英文描述: Single-chip 8-bit microcontroller(8位單片微控制器)
中文描述: 單芯片8位微控制器(8位單片微控制器)
文件頁(yè)數(shù): 28/72頁(yè)
文件大?。?/td> 721K
代理商: P80CE558
Philips Semiconductors
Preliminary specification
P83CE558/P80CE558/P89CE558
Single-chip 8-bit microcontroller
1996 Aug 06
28
6.8
In addition to Timer T2 and the standard timers, a watchdog timer
(T3) consisting of an 11-bit prescaler and an 8-bit timer is also
incorporated (see Figure 27).
Watchdog Timer T3
The timer is incremented every 1.5 ms, derived from the system
clock frequency of 16 MHz by the following:
f
timer
f
CLK
12
2048
When a timer overflow occurs, the microcontroller is reset and a
reset output pulse is generated at pin RSTOUT. Also the PLL control
register is reset.
To prevent a system reset the timer must be reloaded in time by the
application software. If the processor suffers a hardware/software
malfunction, the software will fail to reload the timer. This failure will
produce a reset upon overflow thus preventing the processor
running out of control.
The watchdog timer can only be reloaded if the condition flag
WLE = PCON.4 has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
The time interval between the timer’s reloading and the occurrence
of a reset depends on the reloaded value. For example, this may
range from 1.5 ms to 0.375 s when using an oscillator frequency of
16 MHz.
In the Idle state the watchdog timer and reset circuitry remain active.
The watchdog timer is controlled by the watchdog enable pin (EW).
A LOW level enables the watchdog timer and disables the
Power-down Mode. A HIGH level disables the watchdog timer and
enables the Power-down Mode.
Figure 27. Watchdog timer.
Internal Bus
Timer T3
(8-bit)
LOAD LOADEN
Prescaler
(11-bit)
Clear
f
CLK
/12
EW
WLE
Clear
PD
LOADEN
Internal Bus
Write T3
PCON.4
PCON.1
to reset circuitry (see Figure 46)
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