參數(shù)資料
型號: P80C592
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontroller with on-chip CAN
中文描述: 8位微控制器芯片的CAN
文件頁數(shù): 7/108頁
文件大小: 650K
代理商: P80C592
1996 Jun 27
7
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xC592
Table 1
Pin description for
single function
pins (SOT188-2; see note 1)
Notes
1.
2.
3.
4.
5.
To avoid a ‘latch up’ effect at power-on: V
SS
0.5 V < ‘voltage on any pin at any time’ < V
DD
+ 0.5 V.
Triggered by a rising edge. ADC operation can also be started by software.
RST also provides a reset pulse as output when timer T3 overflows or after a CAN wake-up from Power-down.
ALE is activated every six oscillator periods. During an external data memory access one ALE pulse is skipped.
See Section 7.1, Table 3 for EA operation. For P83Cxxx microcontrollers specified with the option ‘ROM-code
protection’, the EA pin is latched during reset and is ‘don't care’ after reset, regardless of whether the ROM-code
protection is selected or not.
SYMBOL PIN
DESCRIPTION
V
DD
STADC
PWM0
PMW1
EW
2
3
4
5
6
Power supply,
digital part (+5 V). For normal operation and power reduced modes.
Start ADC operation.
Input starting analog-to-digital conversion (note 2). This pin must not float.
Pulse width modulation output 0.
Pulse width modulation output 1.
Enable Watchdog Timer (WDT):
enable for T3 Watchdog Timer and disable Power-down mode.
This pin must not float.
Reset:
input to reset the P8xC592 (note 3).
CAN ground potential
for the CAN transmitter outputs.
Crystal pin 2:
output of the inverting amplifier that forms the oscillator.
When an external clock oscillator is used this pin is left open-circuit.
Crystal pin 1:
input to the inverting amplifier that forms the oscillator, and input to the internal clock
generator. Receives the external clock oscillator signal, when an external oscillator is used.
Ground
, digital part.
Program Store Enable:
Read strobe to external Program Memory (active LOW).
Drive: 8
×
LSTTL inputs.
Address Latch Enable:
latches the Low-byte of the address during accesses to external memory
(note 4). Drive: 8
×
LSTTL inputs; handles CMOS inputs without an external pull-up.
External Access input.
See note 5.
1
2
AV
DD
reference voltage
output respectively input (note 6).
Inputs from the CAN-bus line
to the differential input comparator of the on-chip CAN-controller
(note 7).
RST
CV
SS
XTAL2
15
22
33
XTAL1
34
V
SS
PSEN
35
44
ALE
45
EA
REF
CRX1
CRX0
AV
REF
AV
REF+
AV
SS
AV
DD
46
55
56
57
58
59
60
61
Low-end of ADC
(analog-to-digital) conversion reference resistor.
High-end of ADC
(analog-to-digital) conversion reference resistor (note 8).
Ground
, analog part. For ADC, CAN receiver and reference voltage.
Power supply
, analog part (+5 V). For ADC, CAN receiver and reference voltage.
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