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參數(shù)資料
| 型號： | P80C592 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit microcontroller with on-chip CAN |
| 中文描述： | 8位微控制器芯片的CAN |
| 文件頁數(shù)： | 38/108頁 |
| 文件大?。?/td> | 650K |
| 代理商： | P80C592 |
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1996 Jun 27
38
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xC592
Notes to the description of the SR bits
1.
When the Bus Status bit is set HIGH (Bus-OFF), the CAN-controller will set the Reset Request bit HIGH (present).
It will stay in this state until the CPU sets the Reset Request bit LOW (absent). Once this is completed the
CAN-controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) before setting
the Bus Status bit LOW (Bus-ON), the Error Status bit LOW (ok) and resetting the Error Counters. During Bus-OFF
the output drivers are switched off (floating); external transceiver circuits should output a recessive level in this case.
2.
If both the Receive Status and Transmit Status bits are LOW (idle) the CAN-bus is idle.
3.
If the CPU tries to write to the Transmit Buffer when the Transmit Buffer Access bit is LOW (locked), the written bytes
will not be accepted and will be lost without this being signalled. The Transmission Complete Status bit is set LOW
(incomplete) whenever the Transmission Request bit is set HIGH (present). If an Abort Transmission command is
issued, the Transmit Buffer will be released. If the message, which was requested and then aborted, was not
transmitted, the Transmission Complete Status bit will remain LOW.
4.
If Data Overrun = HIGH (overrun) is detected, the currently received message is dropped. A transmitted message,
granted acceptance, is also stored in a Receive Buffer. This occurs because it is not known if the CAN-controller will
lose arbitration and so become a receiver of the message. If no Receive Buffer is available, Data Overrun is
signalled. However, this transmitted and accepted message does neither cause a Receive Interrupt nor set the
Receive Buffer Status bit to HIGH (full). Also, a Data Overrun does not cause the transmission of an Overload Frame
(see Sections 13.6.1 and 13.6.5).
5.
If the command bit Release Receive Buffer is set HIGH (released) by the CPU, the Receive Buffer Status bit is set
LOW (empty) by IML. When a new message is stored in any of the receive buffers, the Receive Buffer Status bit is
set HIGH (full) again.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P80C592FFA | 制造商:NXP Semiconductors 功能描述: |
| P80C592FFA/00,512 | 功能描述:8位微控制器 -MCU 80C51 W/CAN 16MHZ ROMLESS RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P80C592FFA/00,512 | 制造商:NXP Semiconductors 功能描述:8BIT MCU+CAN, SMD, 80C592, PLCC68 |
| P80C592FFA/00,518 | 功能描述:8位微控制器 -MCU SINGLE-CHIP 8-BIT MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P80C592FFA/00 | 制造商:NXP Semiconductors 功能描述:8BIT MCU+CAN SMD 80C592 PLCC68 |
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