參數(shù)資料
型號(hào): P80C562
廠商: NXP Semiconductors N.V.
元件分類(lèi): 8位微控制器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8位微控制器
文件頁(yè)數(shù): 43/52頁(yè)
文件大?。?/td> 299K
代理商: P80C562
1997 Apr 08
43
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
21 AC CHARACTERISTICS
Parameters are valid over operating temperature range and operating supply voltage range unless otherwise specified.
C
L
= 100 pF for Port 0, ALE and PSEN; C
L
= 80 pF for all other outputs unless specified. See Figs 23 to 25.
Note
1.
t
CLK
= 1/f
osc
= one oscillator clock period. If f
osc
= 16 MHz then t
CLK
= 62.5 ns.
SYMBOL
PARAMETER
f
OSC
= 16 MHz
f
OSC
= VARIABLE
UNIT
MIN.
MAX.
MIN.
MAX.
Program memory
t
LL
t
AL
t
LA
t
LIV
t
LC
t
CC
t
CIV
t
CI
t
CIF
t
AIV
t
AFC
ALE pulse duration
address set-up time to ALE
address hold time after ALE
time from ALE to valid instruction input
time from ALE to control pulse PSEN
control pulse duration PSEN
time from PSEN to valid instruction input
input instruction hold time after PSEN
input instruction float delay after PSEN
address to valid instruction input
address float delay after PSEN
85
8
28
23
143
0
150
83
38
208
10
2t
CLK
40
t
CLK
55
t
CLK
35
t
CLK
40
3t
CLK
45
0
4t
CLK
100
3t
CLK
105
t
CLK
25
5t
CLK
105
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
External data memory
t
RR
t
WW
t
AL
t
LA
t
RD
t
DR
t
DFR
t
LD
t
AD
t
LW
t
AW
t
WHLH
t
DWX
t
DW
t
WD
t
AFR
RD pulse duration
WR pulse duration
address set-up time to ALE
address hold time after ALE
RD to valid data input
data hold time after RD
data float delay after RD
time from ALE to valid data input
address to valid data input
time from ALE to RD or WR
time from address to RD or WR
time from RD or WR HIGH to ALE HIGH
data valid to WR transition
data set-up time before WR
data hold time after WR
address float delay after RD
275
275
8
28
0
138
120
23
3
288
13
148
55
350
398
238
103
0
6t
CLK
100
6t
CLK
100
t
CLK
55
t
CLK
35
0
3t
CLK
50
4t
CLK
130
t
CLK
40
t
CLK
60
7t
CLK
150
t
CLK
50
5t
CLK
165
2t
CLK
70
8t
CLK
150
9t
CLK
165
3t
CLK
+ 50
t
CLK
+ 40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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