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參數(shù)資料
| 型號： | P80C552KBB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-chip 8-bit microcontroller |
| 中文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 15/23頁 |
| 文件大?。?/td> | 185K |
| 代理商： | P80C552KBB |
Philips Semiconductors
Product data
80C552/83C552
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
2002 Sep 03
15
AC ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
INPUT
OUTPUT
I
2
C Interface (Refer to Figure 9)
t
HD;STA
t
LOW
t
HIGH
t
RC
t
FC
t
SU;DAT1
t
SU;DAT2
t
SU;DAT3
t
HD;DAT
t
SU;STA
t
SU;STO
t
BUF
t
RD
t
FD
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1
μ
s.
3. Spikes on the SDA and SCL lines with a duration of less than 3 t
CLCL
will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400 pF.
4. t
CLCL
= 1/f
OSC
= one oscillator clock period at pin XTAL1. For 62 ns, 42 ns < t
CLCL
< 285 ns (16 MHz, 24 MHz > f
OSC
> 3.5 MHz) the SI01
interface meets the I
2
C-bus specification for bit-rates up to 100 kbit/s.
START condition hold time
≥
14 t
CLCL
≥
16 t
CLCL
≥
14 t
CLCL
≤
1
μ
s
≤
0.3
μ
s
≥
250ns
≥
250ns
≥
250ns
≥
0ns
≥
14 t
CLCL
≥
14 t
CLCL
≥
14 t
CLCL
≤
1
μ
s
≤
0.3
μ
s
> 4.0
μ
s
1
> 4.7
μ
s
1
> 4.0
μ
s
1
–
2
< 0.3
μ
s
3
> 20 t
CLCL
– t
RD
> 1
μ
s
1
> 8 t
CLCL
> 8 t
CLCL
– t
FC
> 4.7
μ
s
1
> 4.0
μ
s
1
> 4.7
μ
s
1
–
2
< 0.3
μ
s
3
SCL low time
SCL high time
SCL rise time
SCL fall time
Data set-up time
SDA set-up time (before rep. START cond.)
SDA set-up time (before STOP cond.)
Data hold time
Repeated START set-up time
STOP condition set-up time
Bus free time
SDA rise time
SDA fall time
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