參數(shù)資料
型號(hào)： P80C552KBB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Single-chip 8-bit microcontroller
中文描述： 8-BIT, 30 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80
文件頁(yè)數(shù)： 14/23頁(yè)
文件大?。?/td> 185K
代理商： P80C552KBB
Philips Semiconductors
Product data
80C552/83C552
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
2002 Sep 03
14
AC ELECTRICAL CHARACTERISTICS
(Continued)
1, 2
24 MHz version
24 MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
2
Oscillator frequency
3.5
24
MHz
2
ALE pulse width
43
2t
CLCL
–40
t
CLCL
–25
t
CLCL
–25
ns
2
Address valid to ALE low
17
ns
2
Address hold after ALE low
17
ns
2
ALE low to valid instruction in
102
4t
CLCL
–65
ns
2
ALE low to PSEN low
17
t
CLCL
–25
3t
CLCL
–45
ns
2
PSEN pulse width
80
ns
2
PSEN low to valid instruction in
65
3t
CLCL
–60
ns
2
Input instruction hold after PSEN
0
0
ns
2
Input instruction float after PSEN
17
t
CLCL
–25
5t
CLCL
–80
10
ns
2
Address to valid instruction in
128
ns
2
PSEN low to address float
10
ns
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
DW
t
WHQX
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Serial Timing – Shift Register Mode
3
(Test Conditions: T
amb
= 0
°
C to +70
°
C; V
SS
= 0 V; Load Capacitance = 80 pF)
t
XLXL
6
Serial port clock cycle time
t
QVXH
6
Output data setup to clock rising edge
t
XHQX
6
Output data hold after clock rising edge
t
XHDX
6
Input data hold after clock rising edge
t
XHDV
6
Clock rising edge to input data valid
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. These values are characterized but not 100% production tested.
4. t
CLCL
= 1/f
= one oscillator clock period.
t
CLCL
= 41.7ns at f
OSC
= 24 MHz.
3
RD pulse width
150
6t
CLCL
–100
6t
CLCL
–100
ns
4
WR pulse width
150
ns
3
RD low to valid data in
118
5t
CLCL
–90
ns
3
Data hold after RD
0
0
ns
3
Data float after RDxs
55
2t
CLCL
–28
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
ns
3
ALE low to valid data in
183
ns
3
Address to valid data in
210
ns
3, 4
ALE low to RD or WR low
75
175
3t
CLCL
–50
4t
CLCL
–75
t
CLCL
–30
7t
CLCL
–130
t
CLCL
–25
ns
3, 4
Address valid to WR low or RD low
92
ns
4
Data valid to WR transition
12
ns
4
Data before WR
162
ns
4
Data hold after WR
17
ns
3
RD low to address float
0
0
ns
3, 4
RD or WR high to ALE high
17
67
t
CLCL
–25
t
CLCL
+25
ns
5
High time
3
Low time
3
Rise time
3
Fall time
3
17
17
ns
5
17
17
ns
5
5
20
ns
5
5
20
ns
0.5
12t
CLCL
10t
CLCL
–133
2t
CLCL
–60
0
μ
s
ns
283
23
ns
0
ns
283
10t
CLCL
–133
ns
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