- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367700 > P60ARM-GP1N (Zarlink Semiconductor Inc.) Low power, general purpose 32-bit RISC microprocessor PDF資料下載
參數(shù)資料
| 型號(hào)： | P60ARM-GP1N |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁(yè)數(shù)： | 10/120頁(yè) |
| 文件大?。?/td> | 1275K |
| 代理商： | P60ARM-GP1N |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)
P60ARM-B
6
DBE
I
Data bus enable. When
When
DBE
goes HIGH these output drivers are enabled.
DMA and so on.
DBE
is LOW the write data register output drivers are disabled.
DBE
facilitates data bus sharing for
LATEABT
I
Late
HIGH (Late
back. When it is LOW (Early abort) the modified base register is not written back.
must not be changed during the execution of a data access instruction where abort is active.
It is recommended that the Late
abort scheme be used where possible as this scheme will be
used in future ARM processors.
abort. This signal controls the action of the processor on an
abort) the modified base register of an
abort exception. When it is
aborted LDR or STR instruction is written
LATEABT
LOCK
OS8
Locked operation. When
access, and the memory controller must wait until
device to access the memory.
the duration of the locked memory accesses. It is active only during the data swap (SWP)
instruction.
LOCK
is HIGH, the processor is performing a òl(fā)ockedó memory
LOCK
goes LOW before allowing another
LOCK
changes while
MCLK
is HIGH, and remains HIGH for
MCLK
I
Memory clock input. This clock times all ARM60 memory accesses and internal operations.
The clock has two distinct phases -
phase 1
in which
MCLK
(and
nWAIT
) is HIGH. The clock may be stretched indefinitely in either phase to
allow access to slow peripherals or memory. Alternatively, the
with a free running
MCLK
to achieve the same effect.
MCLK
is LOW and
phase 2
in which
nWAIT
input may be used
nBW
OS8
Not byte/word. This is an output signal used by the processor to indicate to the external
memory system when a data transfer of a byte length is required. The signal is HIGH for
word transfers and LOW for byte transfers and is valid for both read and write cycles. The
signal will become valid during phase 2 of the cycle before the one in which the transfer will
take place. It will remain stable throughout phase 1 of the transfer cycle.
nCPI
O4
Not Coprocessor instruction. When ARM60 executes a coprocessor instruction, it will take
this output LOW and wait for a response from the coprocessor. The action taken will depend
on this response, which the coprocessor signals on the
CPA
and
CPB
inputs.
nFIQ
I
Not fast interrupt request. This is an asynchronous interrupt request to the processor which
causes it to be interrupted if taken LOW when the appropriate enable in the processor is
active. The signal is level sensitive and must be held LOW until a suitable response is
received from the processor.
nIRQ
I
Not interrupt request. As
to interrupt the processor when the appropriate enable is active.
nFIQ
, but with lower priority. May be taken LOW asynchronously
nMREQ
O4
Not memory request. This signal, when LOW, indicates that the processor requires memory
access during the following cycle. The signal becomes valid during phase 1, remaining valid
through phase 2 of the cycle preceding that to which it refers.
nOPC
O4
Not op-code fetch. When LOW this signal indicates that the processor is fetching an
instruction from memory; when HIGH, data (if present) is being transferred. The signal
becomes valid during phase 2 of the previous cycle, remaining valid through phase 1 of the
referenced cycle.
Name
Type
Description
Table 1: Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P60ARM-IG | Low power, general purpose 32-bit RISC microprocessor |
| P60ARM-B | Low power, general purpose 32-bit RISC microprocessor |
| P60A | 60W DC-DC Converter P60A-Series |
| P60A12D05P | 60W DC-DC Converter P60A-Series |
| P60A12D12P | 60W DC-DC Converter P60A-Series |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P60ARM-IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Low power, general purpose 32-bit RISC microprocessor |
| P-60AS/A18 | 功能描述:BATTERY NICAD 2/3A 600MAH W/TAB RoHS:否 類別:電池產(chǎn)品 >> 電池，充電式（蓄電池） 系列:- MSDS 材料安全數(shù)據(jù)表:Nickel Metal Hydride Battery MSDS 標(biāo)準(zhǔn)包裝:1,000 系列:TWICELL 電池化學(xué):鎳金屬氫化物 電池大小:AAA 電壓 - 額定:1.2V 容量:930mAh 尺寸/尺寸:- 端接類型:焊片 放電速率:186mA 標(biāo)準(zhǔn)充電電流:100mA 標(biāo)準(zhǔn)充電時(shí)間:16小時(shí) 重量:0.029 磅（13.15g） 裝運(yùn)信息:- 其它名稱:SY153T |
| P60AS302 | 制造商:APEM 功能描述: |
| P60AS632-8C | 制造商:NYLOK 功能描述: |
| P60AS701 | 功能描述:旋鈕開關(guān) 10POS BCD 0.15A 24V RoHS:否 制造商:C&K Components 位置數(shù)量:5 卡片組數(shù)量: 每卡片組極數(shù):2 電流額定值:250 mA 電壓額定值:125 V 指數(shù)角: 觸點(diǎn)類型: 觸點(diǎn)形式:DPST 端接類型:Solder 安裝類型:Panel 觸點(diǎn)電鍍:Silver |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。