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參數(shù)資料
| 型號： | P5Z22V10-7A |
| 英文描述： | Electrically-Erasable PLD |
| 中文描述： | 電可擦除可編程邏輯器件 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 162K |
| 代理商： | P5Z22V10-7A |
Philips Semiconductors
Product specification
P5Z22V10
5V zero power, TotalCMOS
, universal PLD device
1997 May 02
9
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0
°
C
≤
T
amb
≤
+70
°
C; 4.75
≤
V
DD
≤
5.25V
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP.
UNITS
MIN.
MAX.
0.8
V
IL
V
IH
V
I
V
OL
V
OH
I
I
I
OZ
I
DDQ
Input voltage low
Input voltage high
Input clamp voltage
Output voltage low
Output voltage high
Input leakage current
3-Stated output leakage current
Standby current
V
DD
= 4.75V
V
DD
= 5.25V
V
V
V
V
V
μ
A
μ
A
μ
A
mA
mA
mA
pF
pF
pF
2
V
DD
= 4.75V; I
IN
= –18mA
V
DD
= 4.75V; I
OL
= 8mA
V
DD
= 4.75V; I
OL
= –4mA
V
IN
= 0 to V
DD
V
IN
= 0 to V
DD
V
DD
= 5.25V; T
amb
= 0
°
C
V
DD
= 5.25V; T
amb
= 0
°
C @ 1MHz
V
DD
= 5.25V; T
amb
= 0
°
C @ 50MHz
1 pin/time for no longer than 1 second
T
amb
= 25
°
C; f = 1MHz
T
amb
= 25
°
C; f = 1MHz
T
amb
= 25
°
C; f = 1MHz
–1.2
0.5
2.4
–10
–10
10
10
75
2
15
–100
10
12
10
60
1
10
I
DDD1
Dynamic current
I
SC
C
IN
C
CLK
C
I/O
NOTE:
1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V
or ground. These
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be
affected.
Short circuit output current
Input pin capacitance
Clock input capacitance
I/O pin capacitance
–30
5
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0
°
C
≤
T
amb
≤
+70
°
C; 4.75
≤
V
DD
≤
5.25V
SYMBOL
PARAMETER
–7
D
UNIT
MIN.
MAX.
7.5
MIN.
MAX.
10
t
PD
t
SU
t
CO
t
CF
t
H
t
AR
t
ARW
t
ARR
t
SPR
t
WL
t
WH
t
R
t
F
f
MAX1
f
MAX2
f
MAX3
t
EA
t
ER
Capacitance
C
IN
C
OUT
NOTES:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V
DD
or ground. These
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be
affected.
Input or feedback to non-registered output
Setup time from input, feedback or SP to Clock
Clock to output
Clock to feedback
1
Hold time
Asynchronous Reset to registered output
Asynchronous Reset width
Asynchronous Reset recovery time
Synchronous Preset recovery time
Width of Clock LOW
Width of Clock HIGH
Input rise time
Input fall time
Maximum internal frequency
2
Maximum external frequency
1
Maximum clock frequency
1
Input to Output Enable
Input to Output Disable
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
3
4
6.75
2
0
15
8
3
0
15
5
5
5
5
5
5
3
3
3
3
20
20
20
20
1/(t
SU
+ t
CF
)
1/(t
SU
+ t
CO
)
1/(t
WL
+ t
WH
)
200
103
167
143
83
167
9
9
10
10
Input pin capacitance
Output capacitance
10
12
10
12
pF
pF
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