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參數(shù)資料
| 型號： | P5Z22V10-7A |
| 英文描述： | Electrically-Erasable PLD |
| 中文描述： | 電可擦除可編程邏輯器件 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 162K |
| 代理商： | P5Z22V10-7A |
Philips Semiconductors
Product specification
P5Z22V10
5V zero power, TotalCMOS
, universal PLD device
2
1997 May 02
853–1977 18019
FEATURES
Industry’s first TotalCMOS
22V10 – both CMOS design and
process technologies
Fast Zero Power (FZP
) design technique provides ultra-low
power and high speed
–
Static current of less than 75
μ
A
–
Dynamic current 1/10 to 1/1000 that of competing devices
–
Pin-to-pin delay of only 7.5ns
True Zero Power device with no turbo bits or power down
schemes
Function/JEDEC map compatible with
Bipolar UVCMOS EECMOS 22V10s
Multiple packaging options featuring PCB-friendly flow-through
pinouts (SOL and TSSOP)
–
24-pin TSSOP—uses 93% less in-system space than a 28-pin
PLCC
–
24-pin SOL
–
28-pin PLCC with standard JEDEC pin-out
Available in commercial and industrial operating ranges
Advanced 0.5
μ
E
2
CMOS process
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Varied product term distribution with up to 16 product terms per
output for complex functions
Programmable output polarity
Synchronous preset/asynchronous reset capability
Security bit prevents unauthorized access
Electronic signature for identification
Design entry and verification using industry standard CAE tools
Reprogrammable using industry standard device programmers
DESCRIPTION
The P5Z22V10 is the first SPLD to combine high performance with
low power, without the need for “turbo bits” or other power down
schemes. To achieve this, Philips Semiconductors has used their
FZP
design technique, which replaces conventional sense
amplifier methods for implementing product terms (a technique that
has been used in PLDs since the bipolar era) with a cascaded chain
of pure CMOS gates. This results in the combination of low power
and high speed that has previously been unattainable in the PLD
arena. For 3V operation, Philips Semiconductors offers the
P3Z22V10 that offers high speed and low power in a 3V
implementation.
The P5Z22V10 uses the familiar AND/OR logic array structure,
which allows direct implementation of sum-of-products equations.
This device has a programmable AND array which drives a fixed OR
array. The OR sum of products feeds an “Output Macro Cell”
(OMC), which can be individually configured as a dedicated input, a
combinatorial output, or a registered output with internal feedback.
ORDERING INFORMATION
ORDER CODE
PACKAGE
PROPAGATION
DELAY
TEMPERATURE
RANGE
OPERATING RANGE
DRAWING
NUMBER
P5Z22V10-7A
28-pin PLCC
7.5ns
0 to +70
°
C
V
CC
= 5.0V
±
5%
SOT261-3
P5Z22V10-7D
24-pin SOL
7.5ns
0 to +70
°
C
V
CC
= 5.0V
±
5%
SOT137-1
P5Z22V10-7DH
24-pin TSSOP
7.5ns
0 to +70
°
C
V
CC
= 5.0V
±
5%
SOT355-1
P5Z22V10–DA
28-pin PLCC
10ns
0 to +70
°
C
V
CC
= 5.0V
±
5%
SOT261-3
P5Z22V10–DD
24-pin SOL
10ns
0 to +70
°
C
V
CC
= 5.0V
±
5%
SOT137-1
P5Z22V10–DDH
24-pin TSSOP
10ns
0 to +70
°
C
V
CC
= 5.0V
±
5%
SOT355-1
P5Z22V10IDA
28-pin PLCC
10ns
–40 to +85
°
C
V
CC
= 5.0V
±
10%
SOT261-3
P5Z22V10IDD
24-pin SOL
10ns
–40 to +85
°
C
V
CC
= 5.0V
±
10%
SOT137-1
P5Z22V10IDDH
24-pin TSSOP
10ns
–40 to +85
°
C
V
CC
= 5.0V
±
10%
SOT355-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P5Z22V10-7D | Electrically-Erasable PLD |
| P5Z22V10-7DH | Electrically-Erasable PLD |
| P5Z22V10-DA | Electrically-Erasable PLD |
| P5Z22V10-DD | IC-SM-CMOS EPLD |
| P5Z22V10-DDH | Electrically-Erasable PLD |
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