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參數(shù)資料
| 型號： | P3Z22V10IBA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | 3V zero power, TotalCMOS, universal PLD device |
| 中文描述： | EE PLD, 15 ns, PQCC28 |
| 封裝： | PEDESTAL, PLASTIC, SOT-261-3, LCC-28 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 191K |
| 代理商： | P3Z22V10IBA |
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
, universal PLD device
1997 Jul 18
7
Program/Erase Cycles
The P3Z22V10 is 100% testable, erases/programs in seconds, and
guarantees 1000 program/erase cycles.
Output Polarity
Each macrocell can be configured to implement Active-High or
Active-Low logic. Programmable polarity eliminates the need for
external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled under
the control of its associated programmable output enable product
term. When the logical conditions programmed on the output enable
term are satisfied, the output signal is propagated to the I/O pin.
Otherwise, the output buffer is driven into the high-impedance state.
Under the control of the output enable term, the I/O pin can function
as a dedicated input, a dedicated output, or a bi-directional I/O.
Opening every connection on the output enable term will
permanently enable the output buffer and yield a dedicated output.
Conversely, if every connection is intact, the enable term will always
be logically FALSE and the I/O will function as a dedicated input.
Register Feedback Select
When the I/O macrocell is configured to implement a registered
function (S1 = 0) (Figures 3a or 3b), the feedback signal to the AND
array is taken from the Q output.
Bi-directional I/O Select
When configuring an I/O macrocell to implement a combinatorial
function (S1 = 1) (Figures 3c or 3d), the feedback signal is taken
from the I/O pin. In this case, the pin can be used as a dedicated
input, a dedicated output, or a bi-directional I/O.
Power-On Reset
To ease system initialization, all flip-flops will power-up to a reset
condition and the Q output will be low. The actual output of the
P3Z22V10 will depend on the programmed output polarity. The V
CC
rise must be monotonic.
Design Security
The P3Z22V10 provides a special EEPROM security bit that
prevents unauthorized reading or copying of designs programmed
into the device. The security bit is set by the PLD programmer,
either at the conclusion of the programming cycle or as a separate
step, after the device has been programmed. Once the security bit is
set, it is impossible to verify (read) or program the P3Z22V10 until
the entire device has first been erased with the bulk-erase function.
TotalCMOS
Design Technique
for Fast Zero Power
Philips is the first to offer a TotalCMOS
SPLD, both in process
technology and design technique. Philips employs a cascade of
CMOS gates to implement its Sum of Products instead of the
traditional sense amp approach. This CMOS gate implementation
allows Philips to offer SPLDs which are both high performance and low
power, breaking the paradigm that to have low power, you must accept
low performance. Refer to Figure 4 and Table 1 showing the I
DD
vs.
Frequency of our P3Z22V10 TotalCMOS
SPLD.
TYPICAL
I
(mA)
FREQUENCY (MHz)
SP00443
1
Figure 4.
Typical I
DD
vs. Frequency @ V
DD
= 3.3V, 25
°
C (10-bit counter)
Table 1. Typical I
DD
vs. Frequency
V
DD
= 3.3V@25
°
C
FREQ (MHz)
1
10
20
30
40
50
60
70
80
90
100
110
120
130
Typical I
DD
(mA)
0.2
1.5
3.0
4.5
6.0
7.4
8.9
10.4
11.8
13.2
14.5
15.8
17.0
18.2
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