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參數(shù)資料
| 型號： | P3Z22V10-DDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | 3V zero power, TotalCMOS, universal PLD device |
| 中文描述： | EE PLD, 10 ns, PDSO24 |
| 封裝： | 4.40 MM, PLASTIC, SOT-355-1, TSSOP-24 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 191K |
| 代理商： | P3Z22V10-DDH |
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
, universal PLD device
1997 Jul 18
9
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0
°
C
≤
T
amb
≤
+70
°
C; 3.0
≤
V
DD
≤
3.6V
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP.
UNITS
MIN.
MAX.
0.8
V
IL
V
IH
V
I
V
OL
V
OH
Input voltage low
Input voltage high
Input clamp voltage
Output voltage low
Output voltage high
V
DD
= 3.0V
V
DD
= 3.6V
V
V
V
V
V
μ
A
2
V
DD
= 3.0V; I
IN
= –18mA
V
DD
= 3.0V; I
OL
= 8mA
V
DD
= 3.0V; I
OH
= –4mA
V
IN
= 0 to V
DD
V
IN
= V
DD
to 5.5V
2
V
IN
= 0 to V
DD
V
IN
= V
DD
to 5.5V
2
V
DD
= 3.6V; T
amb
= 0
°
C
V
DD
= 3.6V; T
amb
= 0
°
C @ 1MHz
V
DD
= 3.6V; T
amb
= 0
°
C @ 50MHz
1 pin/time for no longer than 1 se-
cond
T
amb
= 25
°
C; f = 1MHz
T
amb
= 25
°
C; f = 1MHz
T
amb
= 25
°
C; f = 1MHz
–1.2
0.5
2.4
–10
–10
–10
–10
I
I
Input leakage current
In ut leakage current
10
10
10
10
45
2
15
I
OZ
3-Stated output leakage current
3-Stated out ut leakage current
μ
A
I
DDQ
Standby current
25
.5
10
μ
A
mA
mA
I
DDD1
Dynamic current
I
SC
Short circuit output current
–15
–100
mA
C
IN
C
CLK
C
I/O
NOTES:
1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V
DD
or ground. These
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be
affected.
2. Does not apply to F7.
Input pin capacitance
Clock input capacitance
I/O pin capacitance
8
12
10
pF
pF
pF
5
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0
°
C
≤
T
amb
≤
+70
°
C; 3.0
≤
V
DD
≤
3.6V
SYMBOL
PARAMETER
–B
–D
UNIT
MIN.
MAX.
15
MIN.
MAX.
10
t
PD
t
SU
t
CO
t
CF
t
H
t
AR
t
ARW
t
ARR
t
SPR
t
WL
t
WH
t
R
t
F
f
MAX1
f
MAX2
f
MAX3
t
EA
t
ER
Capacitance
C
IN
C
OUT
NOTES:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V
DD
or ground. These
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be
affected.
Input or feedback to non-registered output
Setup time from input, feedback or SP to Clock
Clock to output
Clock to feedback
1
Hold time
Asynchronous Reset to registered output
Asynchronous Reset width
Asynchronous Reset recovery time
Synchronous Preset recovery time
Width of Clock LOW
Width of Clock HIGH
Input rise time
Input fall time
Maximum internal frequency
2
Maximum external frequency
1
Maximum clock frequency
1
Input to Output Enable
Input to Output Disable
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
4.5
3.5
10
6
0
17
9
4.5
0
17
5
5
6
6
6
6
3
3
3
3
20
20
20
20
(1/t
SU
+ t
CF
)
(1/t
SU
+ t
CO
)
(1/t
WL
+ t
WH
)
95
69
167
125
80
167
9
9
9
9
Input pin capacitance
Output capacitance
10
10
10
10
pF
pF
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