
L
G
R
Resets
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
70
Resets
MOTOROLA
5.5 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out). There is
an oscillator stabilization delay of 4064 internal processor bus clock
cycles after the oscillator becomes active.
The POR will generate the RST signal which will reset the CPU. If any
other reset function is active at the end of this 4064 cycle delay, the RST
signal will remain in the reset condition until the other reset condition(s)
end.
POR will activate the RESET pin pulldown device connected to the pin.
V
DD
must drop below V
POR
in order for the internal POR circuit to detect
the next rise of V
DD
.
5.6 Computer Operating Properly Reset (COPR)
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to time-out, an internal reset is
generated to reset the MCU. Regardless of an internal or external reset,
the MCU comes out of a COP reset according to the pin conditions that
determine mode selection.
The COP reset function is enabled or disabled by the Mask option (COP)
and is verified during production testing.
The COP Watchdog reset will activate the internal pulldown device
connected to the RESET pin.
5.6.1 Resetting the COP
Preventing a COP reset is done by writing a ‘0’ to the COPR bit. This
action will reset the counter and begin the time-out period again. The
COPR bit is bit 0 of address $3FF0. A read of address $3FF0 will return
user data programmed at that location.