Core Timer
Registers
MC68HC(7)05H12
—
Rev. 1.0
General Release Specification
MOTOROLA
Core Timer
99
L
G
R
last stage of this counter, giving a possible interrupt at the rate of
f
op
/1024. Two additional stages produce the POR function at f
op
/4064.
The timer counter bypass circuitry (available only in Test Mode) is at this
point in the timer chain. This circuit is followed by two more stages, with
the resulting clock (f
op
/16384) driving the real time interrupt circuit. The
RTI circuit consists of three divider stages with a 1 of 4 selector. The
output of the RTI circuit is further divided by eight to drive the mask
optional COP watchdog timer circuit. The RTI rate selector bits, and the
RTI and TOF enable bits and flags are located in the timer control and
status register at location $08.
8.3 Registers
8.3.1 Core Timer Status and Control Register (CTSCR)
The CTSCR contains the timer interrupt flag, the timer interrupt enable
bits, and the real time interrupt rate select bits.
Figure 8-2
shows the
value of each bit in the CTSCR when coming out of reset.
TOF – Timer Over Flow
TOF is a read-only status bit and is set when the 8-bit ripple counter
rolls over from $FF to $00. A CPU interrupt request will be generated
if TOFE is set. Reset clears TOF.
RTIF – Real Time Interrupt Flag
The real time interrupt circuit consists of a three stage divider and a 1
of 4 selector. The clock frequency that drives the RTI circuit is f
op
/2
13
(or f
op
/8192) with three additional divider stages giving a maximum
$0008
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOF
RTIF
TOFE
RTIE
0
0
RT!
RT0
Write:
RTOF
RRTIF
Reset:
0
0
0
0
0
0
1
1
Figure 8-2. Core Timer Status and Control Register (CTSCR)