參數(shù)資料
型號: P2V28S40ATP-8
廠商: Vanguard International Semiconductor Corporation
英文描述: 128Mb SDRAM Specification
中文描述: 128Mb的SDRAM內(nèi)存規(guī)格
文件頁數(shù): 21/51頁
文件大?。?/td> 652K
代理商: P2V28S40ATP-8
128Mb Synchronous DRAM
JULY.2000
Rev.2.2
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Page-20
BURST INTERRUPTION [ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval
is minimum 1 CLK..
CLK
Command
A0-9
A10
BA0,1
DQ
Yi
Qai0
Qaj1 Qbk0
Qbk1
Qaj0
Qbk2
Qal0
Qal1
Qal2
Qal3
READ
READ
READ
READ
Yj
Yk
Yl
0
0
0
0
00
10
00
01
A11
DQM control
Write control
CLK
Command
A0-9
A10
BA0,1
Q
READ
Yi
0
00
Qai0
Write
Yj
0
00
D
Daj0
Daj1
Daj2
Daj3
DQM
A11
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ
should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1
cycle after WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
Read Interrupted by Read (BL=4, CL=3)
相關(guān)PDF資料
PDF描述
P2V28S20ATP-75 128Mb SDRAM Specification
P2V28S20ATP-8 128Mb SDRAM Specification
P2V28S20DTP-7 128Mb SDRAM Specification
P2V28S30ATP-7 128Mb SDRAM Specification
P2V28S30ATP-75 128Mb SDRAM Specification
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