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參數(shù)資料
| 型號： | P2V28S40ATP-8 |
| 廠商： | Vanguard International Semiconductor Corporation |
| 英文描述： | 128Mb SDRAM Specification |
| 中文描述： | 128Mb的SDRAM內(nèi)存規(guī)格 |
| 文件頁數(shù)： | 20/51頁 |
| 文件大?。?/td> | 652K |
| 代理商： | P2V28S40ATP-8 |
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JULY.2000
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Page-19
WRITE
After tRCD from the bank activation, a WRITE command
can be issued. 1st input data is set at the same cycle as the
WRITE. Following (BL -1) data are written into the RAM,
when the Burst Length is BL. The start address is specified
by A0-A9(x4), A0-8(X8), A0-7(X16) and the address se-
quence of burst data is defined by the Burst Type. A WRITE
command may be applied to any active bank, so the row
precharge time (tRP) can be hidden behind continuous in-
put data by interleaving the multiple banks. From the last input
data to the PRE command, the write recovery time (tWR) is
required. When A10 is high at a WRITE command, the
autoprecharge (WRITEA) is performed. Any command (READ,
WRITE, PRE, TBST, ACT) to the same bank is inhibited till the
internal precharge is complete. The internal precharge begins at
tWR after the last input data cycle. (Need to keep tRAS min.) The
next ACT command can be issued after tRP from the internal
precharge timing.
CLK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
Write
Y
1
00
Da0
Da1
Da2
Da3
tRCD
ACT
Xa
Xa
00
Internal precharge starts
A11
Xa
Xa
CLK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
00
Write
Y
00
Write
Y
0
0
10
Da0
ACT
Xb
Xb
10
0
10
tRCD
tRCD
PRE
Xa
A11
Xb
0
Xa
0
00
PRE
0
Da1
Da2
Da3
Db0
Db1
Db2
Db3
tWR
tRP
WRITE with Auto-Precharge (BL=4)
Multi Bank Interleaving WRITE (BL=4)
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