參數(shù)資料
型號： P2V28S20ATP-7
廠商： Vanguard International Semiconductor Corporation
英文描述： 128Mb SDRAM Specification
中文描述： 128Mb的SDRAM內存規(guī)格
文件頁數(shù)： 25/51頁
文件大?。?/td> 652K
代理商： P2V28S20ATP-7
128Mb Synchronous DRAM
JULY.2000
Rev.2.2
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Page-24
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is required from the last data
to PRE command. During write recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CLK
Command
A0-9,11
A10
BA0-1
DQ
Write
Ya
0
00
ACT
Xa
0
00
Da0
Da1
PRE
0
00
ACT
Xa
0
00
tWR
tRP
DQM
CLK
Command
A0-9,11
A10
BA0-1
DQ
Write
Ya
0
00
ACT
Xa
0
00
Da0
Da1
TBST
Write
Yb
0
00
Db0
Db1
Db2
Db3
[Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation.In this case, the write recovery time is not required and the
bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write Interrupted by Terminate (BL=4)
相關PDF資料
PDF描述
P2V28S40ATP-7 128Mb SDRAM Specification
P2V28S40ATP-75 128Mb SDRAM Specification
P2V28S40ATP-8 128Mb SDRAM Specification
P2V28S20ATP-75 128Mb SDRAM Specification
P2V28S20ATP-8 128Mb SDRAM Specification
相關代理商/技術參數(shù)
參數(shù)描述
P2V28S20ATP-75 制造商:VML 制造商全稱:VML 功能描述:128Mb SDRAM Specification
P2V28S20ATP-8 制造商:VML 制造商全稱:VML 功能描述:128Mb SDRAM Specification
P2V28S20DTP-7 制造商:VML 制造商全稱:VML 功能描述:128Mb SDRAM Specification
P2V28S30ATP-7 制造商:VML 制造商全稱:VML 功能描述:128Mb SDRAM Specification
P2V28S30ATP-75 制造商:VML 制造商全稱:VML 功能描述:128Mb SDRAM Specification
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