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參數(shù)資料
| 型號： | P28F001BX-T90 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 128K X 8 FLASH 12V PROM, 90 ns, PDIP32 |
| 封裝： | 0.620 X 1.640 INCH, PLASTIC, DIP-32 |
| 文件頁數(shù)： | 15/33頁 |
| 文件大?。?/td> | 436K |
| 代理商： | P28F001BX-T90 |
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28F001BX-T/28F001BX-B
Power Supply Decoupling
Flash memory power switching characteristics re-
quire careful device coupling. System designers are
interested in 3 supply current issues; standby current
levels (I
SB
), active current levels (I
CC
) and transient
peaks producted by falling and rising edges of CE
Y
.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress transient voltage peaks. Each device
should have a 0.1
m
F ceramic capacitor connected
between its V
CC
and GND, and between its V
PP
and
GND. These high frequency, low inherent-induc-
tance capacitors should be placed as close as pos-
sible to the device. Additionally, for every 8 devices,
a 4.7
m
F electrolytic capacitor should be placed at
the array’s power supply connection between V
CC
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductances.
V
PP
Trace on Printed Circuit Boards
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the V
PP
power sup-
ply trace. The V
PP
pin supplies the memory cell cur-
rent for programming. Use similar trace widths and
layout considerations given to the V
CC
power bus.
Adequate V
PP
supply traces and decoupling will de-
crease V
PP
voltage spikes and overshoots.
V
CC
, V
PP
, RP
Y
Transitions and the
Command/Status Registers
Programming and erase completion are not guaran-
teed if V
PP
drops below V
PPH
. If the V
PP
Status bit of
the Status Register (SR.3) is set to ‘‘1’’, a Clear
Status Register command MUST be issued before
further program/erase attempts are allowed by the
WSM. Otherwise, the Program (SR.4) or Erase
(SR.5) Status bits of the Status Register will be set
to ‘‘1’’ if error is detected. RP
Y
transitions to V
IL
during program and erase also abort the operations.
Data is partially altered in either case, and the com-
mand sequence must be repeated after normal op-
eration is restored. Device poweroff, or RP
Y
tran-
sitions to V
IL
, clear the Status Register to initial val-
ue 80H.
The Command Register latches commands as is-
sued by system software and is not altered by V
PP
or CE
Y
transitions or WSM actions. Its state upon
powerup, after exit from Deep-Powerdown or after
V
CC
transitions below V
LKO
, is FFH, or Read Array
Mode.
After program or erase is complete, even after V
PP
transitions down to V
PPL
, the Command Register
must be reset to read array mode via the Read Array
command if access to the memory array is desired.
Power Up/Down Protection
The 28F001BX is designed to offer protection
against accidental erasure or programming during
power transitions. Upon power-up, the 28F001BX is
indifferent as to which power supply, V
PP
or V
CC
,
powers up first. Power supply sequencing is not re-
quired. Internal circuitry in the 28F001BX ensures
that the Command Register is reset to Read Array
mode on power up.
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PP
is
active. Since both WE
Y
and CE
Y
must be low for a
command write, driving either to V
IH
will inhibit
writes. The Command Register architecture provides
an added level of protection since alteration of mem-
ory contents only occurs after successful completion
of the two-step command sequences.
Finally, the device is disabled, until RP
Y
is brought
to V
IH
, regardless of the state of its control inputs.
This provides an additional level of protection.
28F001BX Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases us-
able battery life because the 28F001BX does not
consume any power to retain code or data when the
system is off.
In addition, the 28F001BX’s Deep-Powerdown mode
ensures extremely low power dissipation even when
system power is applied. For example, laptop and
other PC applications, after copying BIOS to DRAM,
can lower RP
Y
to V
IL
, producing negligible power
consumption. If access to the boot code is again
needed, as in case of a system RESET
Y
, the part
can again be accessed, following the t
PHAV
wakeup
cycle required after RP
Y
is first raised back to V
IH
.
The first address presented to the device while in
powerdown requires time t
PHAV
, after RP
Y
tran-
sitions high, before outputs are valid. Further ac-
cesses follow normal timing. See AC Characteris-
ticsDRead-Only Operations and Figure 12 for more
information.
15
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