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參數(shù)資料
| 型號： | P13914EJ1V0AN00 |
| 英文描述： | uPC8128TB. uPC8151TB. and uPC8152TB Low-Current Silicon MMIC Amplifiers for Cellular/Cordless Telephones |
| 中文描述： | uPC8128TB。 uPC8151TB。和uPC8152TB低電流硅單片放大器的蜂窩/無繩電話 |
| 文件頁數(shù)： | 10/35頁 |
| 文件大小： | 233K |
| 代理商： | P13914EJ1V0AN00 |
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10
Application Note P13914EJ1V0AN00
Design Method
For <2> and <3> above, the 50-
matching circuit of the LC should be designed based on the S parameter of the
IC while also taking into account mounting circuit board elements. However, for <1>, since definite points cannot
be represented on a Smith chart, the following procedure must be used to adjust the values.
First, match the output stage to 50
for a standard.
Next, while using a network analyzer to monitor S12, adjust the mounting position and constants of the
externally attached circuit (LC) so that the isolation can be excellent.
At NEC, excellent isolation was obtained when this procedure was used to adjust the output stage return loss to
the range of 10 to 20 dB.
The circuit constants that appear in these application notes and the data sheets are values for the corresponding
evaluation boards. Since the evaluation boards, which are designed for simple evaluation, occupy considerable
space, they cannot be applied directly in an actual system. The S parameter values (MAG and ANG) and
input/output Smith charts of the ICs themselves are included in the data sheets and in the appendix of this
document for reference by users of matching circuit design. Users should optimize the matching circuit constants
by referring to this explanation and carefully considering these parameters and the mounting circuit board
elements.
The characteristic curves that appear in the data sheets were measured by creating a matching circuit that
emphasizes isolation (<1> Isolation matching). For characteristics in the circuit configurations of <2> and <3>, see
Table 4-1 Measurement Results
in
4.1 Application Characteristics for Various Matching Methods
.
3.3 Test Circuit
To measure the electrical specifications described in the data sheet, a test circuit was used in which a matching
circuit was created by an LC at the output pin. Figure 3-2 shows the test circuit used for these ICs, and Figure 3-3
shows the evaluation board layout.
Figure 3-2. Test Circuit
IN
OUT
50
L1
4
2,3,5
6
1
50
C
1
C
2
C
3
V
CC
C
4
Output matching circuit
C
5
C
6
C
7
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