參數(shù)資料
型號(hào)： ORSO82G5-2FN680I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 80/153頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
32
Table 5. Inserted TOH Values (All 0x) in AUTO_SOH Mode
The TOH values inserted in AUTO_SOH mode are shown in Table 5. If a specic value is not listed in the table, the
bytes are transmitted transparently from the FPGA logic as in the transparent mode. Optionally K2 can be inserted
by the core using the FORCE_RDI_xx control register bits. A1/A2 and B1 insertion can be independently enabled.
The TOH values inserted in AUTO_TOH mode are shown in Table 6. The values are for all STS-1s in the STS-48
frame unless noted otherwise.
Table 6. Inserted TOH Values (All 0x) in AUTO_TOH Mode
The TOH block can perform A1/A2 corruption by inverting the A1/A2 bytes and also can forces B1 errors by invert-
ing the B1 byte. A RDI can be injected by forcing the K2 byte to “00000110”. In SONET mode, all TOH bytes can be
transparently sent from the FPGA as an option. Error and RDI insertion are controlled by software register bits as
shown in the Register Map tables.
Scramble Sub-block
The scrambler scrambles the incoming 32-bit data using the standard SONET polynomial 1 + x
6 + x7. The scram-
bler can be disabled by a software register bit.
32:8 MUX
The MUX block is responsible for converting 32 bits of data at 77.76 MHz to 8 bits of data at 311.04 MHz. It will
contain a small elastic store for clock domain transfer between the write clock from the FPGA to the divide-by-4
clock from the SERDES output clock (XCK311). It is recommended to use the clocking scheme shown to guaran-
A1 = F6
A2 = 28
J0
B1 = calculated,
1st. STS-1
B1 = 00, other STS-1s
E1
F1
D1
D2
D3
H1
H2
H3
B2
K1
K2
D4
D5
D6
D7
D8
D9
D10
D11
D12
S1
M1
E2
A1 = F6
A2 = 28
J0 = STS-1 ID,
every 4th. STS-1
J0 = 00, other STS-1s
B1 = calculated,
1st. STS-1
B1 = 00, other STS-1s
E1 = 00
F1 = link number,
1st. STS-1
F1 = 00, other STS-1s
D1 = 00
D2 = 00
D3 = 00
H1 = 62, 1st. STS-1
H1 = 93 other STS-1s
H2 = 0A, 1st. STS-1
H2 = FF other STS-1s
H3 = 00
B2 = 00
K1 = 00
K2 = 06 for RDI,
K2 = 00 otherwise,
1st. STS-1
K2 = 00, other STS-1s
D4 = 00
D5 = 00
D6 = 00
D7 = 00
D8 = 00
D9 = 00
D10 = 00
D11 = 00
D12 = 00
S1 = 00
M1 = 00
E2 = 00
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ORSO82G5-2FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 2.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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