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參數(shù)資料
| 型號： | OR3T125-5PS208I |
| 英文描述： | Dual 1.8V, 1MHz OP, I temp, -40C to +85C, 8-MSOP, TUBE |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 4/210頁 |
| 文件大?。?/td> | 4663K |
| 代理商： | OR3T125-5PS208I |
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Table of Contents
Page
Contents
Contents
Page
4
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Characteristics ......................................................136
Table 62. Master Parallel Configuration Mode Timing
Characteristics ......................................................137
Table 63. Asynchronous Peripheral Configuration Mode
Timing Characteristics ...........................................138
Table 64. Slave Serial Configuration Mode Timing
Characteristics ......................................................139
Table 65. Slave Parallel Configuration Mode
Timing Characteristics ...........................................140
Table 66. Readback Timing Characteristics ...........142
Table 67. Pin Descriptions ......................................149
Table 68. ORCA I/Os Summary .............................153
Table 69. Series 3 ExpressCLK Pins .....................154
Table 70. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 208-Pin
SQFP/SQFP2 Pinout ............................................155
Table 71. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 240-Pin
SQFP/SQFP2 Pinout ............................................161
Table 72. OR3T20, OR3T30, and OR3C/T55
256-Pin PBGA Pinout ............................................168
Table 73. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 352-Pin PBGA Pinout .172
Table 74. OR3C/T80 and OR3T125 432-Pin
EBGA Pinout .........................................................182
Table 75. OR3T125 600-Pin EBGA Pinout ............187
Table 76. Plastic Package Thermal
Characteristics for the ORCA Series .....................195
Table 77. Package Coplanarity ..............................196
Table 78. Package Parasitics .................................196
Table 79. Voltage Options ......................................206
Table 80. Temperature Options .............................206
Table 81. Package Options ....................................206
Table 82. ORCA Series 3 Package Matrix .............206
Table 83. Speed Grade Options .............................206
Figures
Figure 1. OR3C/T55 Array ........................................10
Figure 2. PFU Ports ..................................................11
Figure 3. Simplified PFU Diagram ............................12
Figure 4. Simplified F4 and F5 Logic Modes ............14
Figure 5. Softwired LUT Topology Examples ...........15
Figure 6. Ripple Mode ..............................................16
Figure 7. Counter Submode .....................................17
Figure 8. Multiplier Submode ....................................18
Figure 9. Memory Mode ...........................................19
Figure 10. Memory Mode Expansion Example—
128 x 8 RAM ...........................................................20
Figure 11. SLIC All Modes Diagram .........................22
Figure 12. Buffer Mode .............................................22
Figure 13. Buffer-Buffer-Decoder Mode ...................23
Figure 14. Buffer-Decoder-Buffer Mode ...................23
Figure 15. Buffer-Decoder-Decoder Mode ...............24
Figure 16. Decoder Mode .........................................24
Figure 17. Latch/FF Set/Reset Configurations .........26
Figure 18. Configurable Interconnect Point ..............27
Figure 19. Single PLC View of Inter-PLC Route
Segments ................................................................28
Figure 20. Multiple PLC View of Inter-PLC Routing .32
Figure 21. PLC Architecture .....................................35
Figure 22. OR3C/Txxx Programmable Input/Output
(PIO) Image from ORCA Foundry ...........................36
Figure 23. Fast-Capture Latch and Timing ...............39
Figure 24. PIO Input Demultiplexing .........................40
Figure 25. Output Multiplexing (OUT1OUT2 Mode) .42
Figure 26. Output Multiplexing
(OUT2OUTREG Mode) ...........................................42
Figure 27. PIC Architecture ......................................46
Figure 28. Interquad Routing ....................................47
Figure 29. hIQ Block Detail .......................................48
Figure 30. Top (TMID) Routing .................................49
Figure 31. PFU Clock Sources .................................50
Figure 32. ORCA Series 3 System Clock
Distribution Overview ..............................................51
Figure 33. PIC System Clock Spine Generation ......52
Figure 34. ExpressCLK and Fast Clock Distribution 53
Figure 35. Top CLKCNTRL Function Block ..............56
Figure 36. Printed-Circuit Board with Boundary-
Scan Circuitry ..........................................................57
Figure 37. Boundary-Scan Interface .........................58
Figure 38. ORCA Series Boundary-Scan Circuitry
Functional Diagram .................................................60
Figure 39. TAP Controller State Transition Diagram 61
Figure 40. Boundary-Scan Cell ................................62
Figure 41. Instruction Register Scan Timing
Diagram ...................................................................63
Figure 42. MPI Block Diagram ..................................64
Figure 43. PowerPC/MPI ..........................................65
Figure 44. i960/MPI ..................................................66
Figure 45. PCM Block Diagram ................................72
Figure 46. PCM Functional Block Diagram ..............74
Figure 47. ExpressCLK Delay Minimization Using
the PCM ..................................................................76
Figure 48. Clock Phase Adjustment Using the PCM 83
Figure 49. FPGA States of Operation .......................85
Figure 50. Initialization/Configuration/Start-Up
Waveforms ..............................................................86
Figure 51. Start-Up Waveforms ................................88
Figure 52. Serial Configuration Data Format—
Autoincrement Mode ...............................................90
Figure 53. Serial Configuration Data Format—
相關PDF資料 |
PDF描述 |
|---|---|
| OR3T125-5PS240I | Dual 1.8V, 1MHz OP, I temp, -40C to +85C, 8-PDIP, TUBE |
| OR3T125-6BC432I | Field Programmable Gate Array (FPGA) |
| OR3T125-6BC600I | Dual 1.8V, 1MHz OP, -40C to +125C, 8-SOIC 150mil, T/R |
| OR3T125-6PS208I | Field Programmable Gate Array (FPGA) |
| OR3T125-6PS240I | Field Programmable Gate Array (FPGA) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-5PS240 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-5PS240I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-6BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1256BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-6BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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