參數(shù)資料
型號(hào)： OQ8844
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： Digital Servo Driver DSD-2
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO20
文件頁(yè)數(shù)： 7/16頁(yè)
文件大?。?/td> 80K
代理商： OQ8844
1995 Nov 27
7
Philips Semiconductors
Product specification
Digital Servo Driver (DSD-2)
OQ8844
Fig.7 Amplitude transfer.
MBG790
|H|
1/2fs
Fig.8 Idling pattern.
MBG791
M
Iidle
(1)
VDD
VSS
TIMING
1-bit
code
'idle'
clock
A
B
C
D
(1) Sledge motor; focus/radial motor.
Switches
The digital part of the power drivers consists of standard
cells. The power switches are specifically designed for CD
applications. The most important feature is their
on-resistance. In the applications, they have to drive very
low-ohmic actuators and/or motors. The switches are
designed to have an on-resistance of 2
for the actuator
drivers and 1
for the sledge motor driver. In any mode,
there are always two switches in series with the
actuator/motor. The total loss due to the switches is 4
for
the actuators and 2
for the sledge motor.
Timing of input and output signals
All internal timing signals are derived from the externally
supplied CLI signal.
Sampling of the data inputs (SLC, FOC and RAC) occurs
at a frequency of
1
4
CL. For each channel, the clocking-in
occurs at a different positive edge of CLI. Because there
are only 3 channels, and the clock frequency CLI is
divided-by-4, only 3 out of 4 positive edges are effective for
sampling one of the inputs.
The switching of the outputs occurs in a similar way,
except that in this event the negative edge of CLI is used.
In this way, the input signals are immune to the noise
radiated by the switching of the outputs. It is possible that
an output transition will have a noticeable effect on the
power supply voltage or the ground voltage. To avoid
simultaneous transitions of all outputs, the outputs of each
bridge are also clocked at a different phase of CLI.
Consequentially there are only 3 out of 4 negative edges
effective.
To reset the circuit, both the reset condition and the clock
should be present, because all flip-flops are reset
synchronously. The clock signal is also required to obtain
one of the possible modes of operation indicated in
Table 1.
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