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參數(shù)資料
| 型號： | OQ8844 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Digital Servo Driver DSD-2 |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 80K |
| 代理商： | OQ8844 |
1995 Nov 27
5
Philips Semiconductors
Product specification
Digital Servo Driver (DSD-2)
OQ8844
FUNCTIONAL DESCRIPTION
Principle of a class-D digital power driver
Figure 3 shows the block diagram of one of the digital
drivers integrated in the DSD2. It consists of a timing block
and four CMOS switches. The input signal is a 1-bit Pulse
Density Modulated (PDM) signal, the output of the digital
servo ICs.
The maximum operating clock frequency of the device is
5 MHz. With the mentioned digital servo ICs, the operating
frequency of the digital drivers is 4.2336 MHz
(96
×
44.1 kHz). The sampling frequency of the 1-bit code
however is 1.0584 MHz, so internally in the DSD2 the
clock speed of the switches will be 1.0584 MHz.
The higher input clock frequency is used to make
non-overlapping pulses to prevent short-circuits between
the supply voltages. For the control of the switches, two
states can be distinguished. If the 1-bit code contains a
logic 1, switches A and D are closed and current will flow
in the direction as shown in Fig.4.
If the 1-bit code contains a logic 0, switches B and C are
closed and current will flow in the opposite direction, as
shown in Fig.5.
This indicates that the difference between the mean
number of ones and zeros in the PDM signal determines
the direction in which the actuator or motor will rotate.
If the mean number of ones and zeros is equal (Idle mode)
the current through the motor or actuator is alternated
between the positive and negative direction at a speed of
half the sample frequency of 1.0584 MHz. This results in a
high dissipation and the motor does not move.
To improve the efficiency, a digital notch filter is added at
the input of the digital drivers. This filters the Idle mode
pattern (1010101010 etc.) see Fig.6.
The amplitude transfer as a function of frequency is given
in Fig.7.
Figure 7 shows that the filter has a zero on
1
2
f
s
,
consequentially filtering out the idle pattern (101010).
The output of this filter is a three-level code (1.5-bit).
For the control of the switches three states (1.5-bit) can be
distinguished: the two states as described earlier and a
third one. This state is used when an idling pattern is
supplied.
Switches C and D are closed (see Fig.8). In this idle mode,
no current will flow and thus the efficiency will be improved.
This mode is also used to short-circuit the inductive
actuator/motor. In this way, high induction voltages are
prevented because the current can commutate via the
filter and the short-circuit in the switches. All three drivers
(radial, focus and sledge) contain a digital notch filter as
described. Each driver has its own power supply pins to
reduce crosstalk because of the relative high current
flowing through the pins.
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