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參數(shù)資料
| 型號： | OPA687 |
| 英文描述： | Wideband, Ultra-Low Noise, Voltage Feedback OPERATIONAL AMPLIFIER With Power Down |
| 中文描述： | 寬帶，超低噪聲，電壓反饋運算放大器打倒電源 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 172K |
| 代理商： | OPA687 |
14
OPA687
predict the intermodulation spurious for two closely-spaced
frequencies. If the two test frequencies, f
1
and f
2
, are
specified in terms of average and delta frequency, f
O
= (f
1
+
f
2
)/2 and
f = |f
2
– f
1
|/2, the two, 3-order, close-in spurious
tones will appear at f
O
±
3
f. The difference between two
equal test-tone power levels and these intermodulation spu-
rious power levels is given by (dBc = 2 (IM3 – P
O
)) where
IM3 is the intercept taken from the Typical Performance
Curve and P
O
is the power level in dBm at the 50
load for
one of the two, closely-spaced test frequencies. For instance,
at 20MHz, the OPA687—at a gain of +20, has an intercept
of 43dBm at a matched 50
load. If the full envelope of the
two frequencies needs to be 2Vp-p, this requires each tone
to be 4dBm. The 3rd-order intermodulation spurious tones
will then be 2 (43 – 4)=78dBc below the test-tone power
level (–74dBm). If this same 2Vp-p, 2-tone envelope were
delivered directly into the input of an ADC without the
matching loss or the loading of the 50
network, the
intercept would increase to at least 49dBm. With the same
signal and gain conditions, but now driving directly into a
light load, the spurious tones will then be at least 2 (49 –
4) = 90dBc below the 4dBm test-tone power levels centered
on 20MHz. Tests have shown that, in reality, they are much
lower due to the lighter loading presented by most ADCs.
DC ACCURACY AND OFFSET CONTROL
The OPA687 can provide excellent DC signal accuracy due
to its high open-loop gain, high common-mode rejection,
high power supply rejection, and low input offset voltage
and bias current offset errors. To take full advantage of its
low
±
1.0mV input offset voltage, careful attention to input
bias current cancellation is also required. The low noise
input stage for the OPA687 has a relatively high input bias
current (20
μ
A typ into the pins) but with a very close match
between the two input currents—typically
±
200nA input
offset current. The total output offset voltage may be consid-
erably reduced by matching the source impedances looking
out of the two inputs. For example, one way to add bias
current cancellation to the circuit of Figure 1 would be to
insert a 12.1
series resistor into the non-inverting input
from the 50
terminating resistor. When the 50
source
resistor is DC-coupled, this will increase the source imped-
ance for the non-inverting input bias current to 37.1
. Since
this is now equal to the impedance looking out of the
inverting input (R
F
|| R
G
) for Figure 1, the circuit will cancel
the gains for the bias currents to the output leaving only the
offset current times the feedback resistor as a residual DC
error term at the output. Using the 750
feedback resistor,
this output error will now be less than
±
1.8
μ
A 750
=
±
1.4mV over the full temperature range for the circuit of
Figure 1 with a 12.1
resistor added as described. The
output DC offset will then be dominated by the input offset
voltage multiplied by the signal gain. For the circuit of
Figure 1, this will give a worst-case output DC offset of
±
1.6mV 20 =
±
32mV over the full temperature range.
A fine-scale output offset null, or DC operating point adjust-
ment is sometimes required. Numerous techniques are avail-
able for introducing a DC offset control into an op amp
circuit. Most of these techniques eventually reduce to setting
up a DC current through the feedback resistor. One key
consideration to selecting a technique is to insure that it has
a minimal impact on the desired signal path frequency
response. If the signal path is intended to be non-inverting,
the offset control is best applied as an inverting summing
signal to avoid interaction with the signal source. If the
signal path is intended to be inverting, applying the offset
control to the non-inverting input can be considered. For a
DC-coupled inverting input signal, this DC offset signal will
set up a DC current back into the source that must be
considered. An offset adjustment placed on the inverting op
amp input can also change the noise gain and frequency
response flatness. Figure 8 shows one example of an offset
adjustment for a DC-coupled signal path that will have
minimum impact on the signal frequency response. In this
case, the input is brought into an inverting gain resistor with
the DC adjustment and additional current summed into the
inverting node. The resistor values setting this offset adjust-
ment are much larger than the signal path resistors. This will
insure that this adjustment has minimal impact on the loop
gain and hence, the frequency response.
FIGURE 8. DC-Coupled, Inverting Gain of –40, with Offset
Adjustment.
R
F
2k
±
250mV Output Adjustment
= – R
G
Supply Decoupling
Not Shown
5k
5k
95.3
0.1
μ
F
R
G
50
V
I
20k
10k
0.1
μ
F
–5V
+5V
OPA687
+5V
–5V
V
O
V
O
V
I
R
F
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PDF描述 |
|---|---|
| OPA688U | Unity Gain Stable, Wideband VOLTAGE LIMITING AMPLIFIER |
| OPA688P | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| OPA688 | Unity Gain Stable, Wideband VOLTAGE LIMITING AMPLIFIER |
| OPA689U | Wideband, High Gain VOLTAGE LIMITING AMPLIFIER |
| OPA689P | Wideband, High Gain VOLTAGE LIMITING AMPLIFIER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OPA687N | 制造商:BB 制造商全稱:BB 功能描述:Wideband, Ultra-Low Noise, Voltage Feedback OPERATIONAL AMPLIFIER With Power Down |
| OPA687N/250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
| OPA687N/3K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
| OPA687U | 制造商:Rochester Electronics LLC 功能描述:OP AMP,HIGH SPEED VFB W/PWR DOWN - Bulk |
| OPA687U/2K5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
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