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參數(shù)資料
| 型號(hào)： | OPA680P |
| 英文描述： | Wideband, Voltage Feedback OPERATIONAL AMPLIFIER With Disable TM |
| 中文描述： | 寬帶，電壓反饋運(yùn)算放大器，禁用商標(biāo) |
| 文件頁數(shù)： | 19/21頁 |
| 文件大?。?/td> | 235K |
| 代理商： | OPA680P |
19
OPA680
eventually turning on those two diodes (
≈
100
μ
A). At this
point, any further current pulled out of V
DIS
goes through
those diodes holding the emitter-base voltage of Q1 at
approximately zero volts. This shuts off the collector cur-
rent out of Q1, turning the amplifier off. The supply current
in the disable mode are only those required to operate the
circuit of Figure 13. Additional circuitry ensures that turn-
on time occurs faster than turn-off time (make-before-
break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA680 is operating in a gain of +1,
this will show a very high impedance at the output and
exceptional signal isolation. If operating at a gain greater
than +1, the total feedback network resistance (R
F
+ R
G
)
will appear as the impedance looking back into the output,
but the circuit will still show very high forward and reverse
isolation. If configured as an inverting amplifier, the input
and output will be connected through the feedback network
resistance (R
F
+ R
G
) and the isolation will be very poor as
a result.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 14
shows these glitches for the circuit of Figure 1 with the
input signal at 0V. The glitch waveform at the output pin is
plotted along with the DIS pin voltage.
DISABLE OPERATION
The OPA680 provides an optional disable feature that may
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA680 will operate normally.
To disable, the control pin must be asserted LOW. Figure 13
shows a simplified internal circuit for the disable control
feature.
FIGURE 13. Simplified Disable Control Circuit.
25k
110k
15k
I
Control
–V
S
+V
S
V
DIS
Q1
R
F
1k
±200mV Output Adjustment
= – R
G
Supply Decoupling
Not Shown
5k
5k
328
0.1μF
R
G
500
V
I
20k
10k
0.1μF
–5V
+5V
OPA680
+5V
–5V
V
O
V
O
V
I
R
F
FIGURE 12. DC-Coupled, Inverting Gain of –2, with Offset
Adjustment.
FIGURE 14. Disable/Enable Glitch.
40
20
0
–20
–40
Time (20ns/div)
O
Output Voltage
(0V Input)
V
DIS
0.2V
4.8V
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 14, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
DIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 1k
series resistor between the
logic gate and the DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
DIS pin while still ensuring adequate logic level swing.
In normal operation, base current to Q1 is provided through
the 110k
resistor, while the emitter current through the
15k
resistor sets up a voltage drop that is inadequate to
turn on the two diodes in Q1’s emitter. As V
DIS
is pulled
LOW, additional current is pulled through the 15k
resistor
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