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參數(shù)資料
| 型號(hào)： | OPA680 |
| 英文描述： | Wideband, Voltage Feedback OPERATIONAL AMPLIFIER With Disable TM |
| 中文描述： | 寬帶，電壓反饋運(yùn)算放大器，禁用商標(biāo) |
| 文件頁(yè)數(shù)： | 20/21頁(yè) |
| 文件大?。?/td> | 235K |
| 代理商： | OPA680 |
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OPA680
THERMAL ANALYSIS
Due to the high output power capability of the OPA680,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175
°
C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
θ
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in
the output stage (P
DL
) to deliver load power. Quiescent
power is simply the specified no-load supply current times
the total supply voltage across the part. P
DL
will depend on
the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition, P
DL
= V
S2
/(4R
L
)
where R
L
includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA680N (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85
°
C and driving a grounded 20
load.
P
D
= 10V7.2mA + 5
2
/(4(20
|| 804
)) = 392mW
Maximum T
J
= +85
°
C + (0.39W150
°
C/W) = 144
°
C.
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower guaranteed junction temperatures. The highest
possible internal dissipation will occur if the load requires
current to be forced into the output for positive output
voltages or sourced from the output for negative output
voltages. This puts a high current through a large internal
voltage drop in the output transistors. The output V-I plot
shown in the Typical Performance Curves include a bound-
ary for 1W maximum internal power dissipation under these
conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA680 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a)
Minimize parasitic capacitance
to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b)
Minimize the distance
(<0.25") from the power supply
pins to high frequency 0.1
μ
F decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections should always be decoupled with these capaci-
tors. An optional supply decoupling capacitor (0.1
μ
F) across
the two power supplies (for bipolar operation) will improve
2nd harmonic distortion performance. Larger (2.2
μ
F to
6.8
μ
F) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may be
placed somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
c)
Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA680.
Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter over-
all layout. Metal film or carbon composition axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads and PC board traces as short as
possible. Never use wirewound type resistors in a high
frequency application. Since the output pin and inverting
input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as non-inverting input termination resis-
tors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external resis-
tors, excessively high resistor values can create significant
time constants that can degrade performance. Good axial
metal film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values >1.5k
,
this parasitic capacitance can add a pole and/or zero below
500MHz that can effect circuit operation. Keep resistor
values as low as possible consistent with load driving con-
siderations. The 402
feedback used in the typical perfor-
mance specifications is a good starting point for design.
Note that a 25
feedback resistor, rather than a direct short,
is suggested for the unity gain follower application. This
effectively isolates the inverting input capacitance from the
output pin that would otherwise cause an additional peaking
in the gain of +1 frequency response.
d) Connections to other wideband devices
on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
S
from the
plot of Recommended R
S
vs Capacitive Load. Low parasitic
capacitive loads (<5pF) may not need an R
S
since the
OPA680 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an
R
S
are allowed as the signal gain increases (increasing the
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OPA680N | 制造商:BB 制造商全稱:BB 功能描述:Wideband, Voltage Feedback OPERATIONAL AMPLIFIER With Disable TM |
| OPA680N/250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
| OPA680N/3K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
| OPA680P | 功能描述:高速運(yùn)算放大器 Wideband V Feedb RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補(bǔ)償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| OPA680U | 制造商:BB 制造商全稱:BB 功能描述:EVALUATION FIXTURE |
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