
12
OPA680
output voltage can swing to within 1V of either supply pin
while delivering >100mA output current. A demanding 100
load to a midpoint bias is used in this characterization circuit.
The new output stage circuit used in the OPA680 can deliver
large bipolar output currents into this midpoint load with
minimal crossover distortion, as shown in the +5V supply, 3rd
harmonic distortion plots.
SINGLE SUPPLY A/D CONVERTER INTERFACE
Most modern, high performance analog-to-digital converters
(such as the Burr-Brown ADS8xx and ADS9xx series) operate
on a single +5V (or lower) power supply. It has been a
considerable challenge for single supply op amps to deliver a
low distortion input signal at the ADC input for signal frequen-
cies exceeding 5MHz. The high slew rate, exceptional output
swing and high linearity of the OPA680 make it an ideal single
supply ADC driver. The circuit on the front page shows one
possible interface. Figure 3 shows the test circuit of Figure 2
modified for a capacitive (A/D) load and with an optional
output pull-down resistor (R
B
).
The OPA680 in the circuit of Figure 3 provides >200MHz
bandwidth for a 2Vp-p output swing. Minimal 3rd harmonic
distortion or two-tone, 3rd-order intermodulation distortion
will be observed due to the very low crossover distortion in the
OPA680 output stage. The limit of output Spurious Free
Dynamic Range (SFDR) will be set by the 2nd harmonic
distortion. Without R
B
, the circuit of Figure 3 measured at
10MHz shows an SFDR of 65dBc. This may be improved by
pulling additional DC bias current (I
B
) out of the output stage
through the optional R
B
resistor to ground (the output midpoint
is at 2.5V for Figure 3). Adjusting I
B
gives the improvement in
SFDR shown in Figure 4. SFDR improvement is achieved for
I
B
values up to 6mA, with worse performance for higher
values.
73
72
71
70
69
68
67
66
65
Output Pull-Down Current (mA)
0
1
2
3
4
5
6
7
8
9
10
S
V
O
= 2Vp-p, 10MHz
FIGURE 4. SFDR vs I
B
.
HIGH PERFORMANCE DAC TRANSIMPEDANCE
AMPLIFIER
High frequency DDS DACs require a low distortion
output amplifier to retain their SFDR performance into
real-world loads. A single-ended output drive imple-
mentation is shown in Figure 5. In this circuit, only one
side of the complementary output drive signal is used.
The diagram shows the signal output current connected
into the virtual ground summing junction of the OPA680,
which is set up as a transimpedance stage or “I-V
converter”. The unused current output of the DAC is
connected to ground. If the DAC requires its outputs
terminated to a compliance voltage other than ground
for operation, the appropriate voltage level may be
applied to the non-inverting input of the OPA680. The
FIGURE 3. Single-Supply ADC Input Driver.
OPA680
402
50
402
59
1Vp-p
698
698
V
I
+5V
DIS
0.1μF
R
S
30
I
B
R
B
50pF
0.1μF
2.5V DC
±1V AC
ADC Input
Power supply decoupling not shown