
13
OPA2652
placed directly on the output pin. When the amplifier’s
open-loop output resistance is considered, this capacitive
load introduces an additional pole in the signal path that can
decrease the phase margin. Several external solutions to this
problem have been suggested. When the primary consider-
ations are frequency response flatness, pulse response fidel-
ity and/or distortion, the simplest and most effective solution
is to isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds a
zero at a higher frequency. The additional zero acts to cancel
the phase lag from the capacitive load pole, thus increasing
the phase margin and improving stability.
The Typical Performance Curves show the recommended
R
S
versus capacitive load and the resulting frequency re-
sponse at the load. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the OPA2652.
Long PC board traces, unmatched cables, and connections to
multiple devices can easily exceed this value. Always con-
sider this effect carefully, and add the recommended series
resistor as close as possible to the OPA2652 output pin (see
Board Layout Guidelines).
DISTORTION PERFORMANCE
The OPA2652 provides good distortion performance into a
100
load on
±
5V supplies. Increasing the load impedance
improves distortion directly. Remember that the total load
includes the feedback network; in the non-inverting configu-
ration (Figure 1) this is sum of R
F
+ R
G
, while in the
inverting configuration, it is just R
F
. Also, providing an
additional supply decoupling capacitor (0.1
μ
F) between the
supply pins (for bipolar operation) improves the 2nd-order
distortion slightly (3dB to 6dB).
It is also true that increasing the output voltage swing
increases harmonic distortion.
NOISE PERFORMANCE
The OPA2652 input-referred voltage noise (8nV/
√
Hz), and
the two input-referred current noise terms (1.4pA/
√
Hz), com-
bine to give low output noise under a wide variety of operating
conditions. Figure 8 shows the op amp noise analysis model
with all the noise terms included. In this model, all noise terms
are taken to be noise voltage or current density terms in either
nV/
√
Hz or pA/
√
Hz.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the
output noise voltage using the terms shown in Figure 10.
Equation 1:
Dividing this expression by the noise gain (NG = 1+R
F
/R
G
)
will give the equivalent input-referred spot noise voltage at
the non-inverting input, as shown in Equation 2.
Equation 2:
Evaluating these two equations for the OPA2652 circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 17nV/
√
Hz and a total equivalent input
spot noise voltage of 8.4nV/
√
Hz. This is including the noise
added by the bias current cancellation resistor (205
) on the
non-inverting input. This total input-referred spot noise
voltage is only slightly higher than the 8nV/
√
Hz specifica-
tion for the op amp voltage noise alone. This will be the case
as long as the impedances appearing at each op amp input
are limited to the previously recommend maximum value of
300
. Keeping both (R
F
|| R
G
) and the non-inverting input
source impedance less than 300
will satisfy both noise and
frequency response flatness considerations. Since the resis-
tor-induced noise is relatively negligible, additional capaci-
tive decoupling across the bias current cancellation resistor
(R
B
) for the inverting op amp configuration of Figure 2 is not
required.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage feedback op
amp allows good output DC accuracy in a wide variety of
applications. Although the high speed input stage does
require relatively high input bias current (typically 4
μ
A out
of each input terminal), the close matching between them
may be used to significantly reduce the output DC error
caused by this current. This is done by matching the DC
source resistances appearing at the two inputs. This reduces
the output DC error due to the input bias currents to the
offset current times the feedback resistor. Evaluating the
configuration of Figure 1, using worst-case +25
°
C input
offset voltage and current specifications, gives a worst-case
output offset voltage equal to:
±
(NG V
OS(MAX)
)
±
(R
F
I
OS(MAX)
)
=
±
(1.94 7.0mV)
±
(402
1.0
μ
A)
=
±
14.0mV
(NG = non-inverting signal gain)
A fine scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp
E
N
=
E
NI
2
+
I
BN
R
S
(
)
2
+ 4
kTR
S
+
I
BI
R
F
NG
2
+4
kTR
F
NG
E
O
=
E
NI
2
+
I
BN
R
S
(
)
2
+ 4
kTR
S
(
)
NG
2
+
I
BI
R
F
(
)
2
+ 4
kTR
F
NG
4kT
R
G
R
G
R
F
R
S
1/2
OPA2652
I
BI
E
O
I
BN
4kT = 1.6x10
–20
J
at 290
°
K
E
RS
E
NI
4kTR
S
√
4kTR
F
√
FIGURE 8. Op Amp Noise Analysis Model.