
2002 Jan 17
33
Philips Semiconductors
Product specification
48
×
84 dot matrix LCD driver
OM6211
18.7
Programming flow
Programming is achieved whilst in CALMM mode and with
the application of the programming voltages. As
mentioned previously, the data for programming the OTP
cell is contained in the corresponding shift register cell.
The shift register cell must be loaded with a logic 1 in order
to program the corresponding OTP cell. If the shift register
cell contains a logic 0, then no action will take place when
the programming voltages are applied.
Once programmed, an OTP cell can not be
un-programmed. An already programmed cell, that is an
OTP cell containing a logic 1, must not be re-programmed.
The order for programming cells is not significant.
However, it is recommended that the seal bit is
programmed last.
Once this bit has been programmed it will not be possible
to re-enter the CALMM mode.
During programming a substantial current flows in the
V
LCDIN
pin. For this reason it is recommended to program
only one OTP cell at a time. This is achieved by filling all
but one shift register cells with logic 0. It should be noted
thattheprogrammingspecificationreferstothevoltagesat
the chip pins, contact resistance must therefore be
considered by the user.
An example sequence of commands and data for OTP
programming is shown in Table 13.
It is assumed that the OM6211 has just been reset.
Table 13
Example sequence for OTP programming; note 1
Note
1.
X = don’t care.
STEP
D/C
COMMAND BYTE
ACTION
DB7
1
1
DB6
1
0
DB5
1
1
DB4
0
0
DB3
1
1
DB2
0
1
DB1
1
1
DB0
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0
0
send Enable OTP command
exit Power-down (e.g. DON = 1)
wait 5 ms for refresh to take effect
re-enter Power-down (DON = 0)
enter CALMM mode
shift in data. MMOTPVOP
7
MMOTPVOP
6
MMOTPVOP
5
MMOTPVOP
4
(the only bit with the value 1)
MMOTPVOP
3
MMOTPVOP
2
MMOTPVOP
1
MMOTPVOP
0
MMVOPCAL
4
MMVOPCAL
3
MMVOPCAL
2
MMVOPCAL
1
MMVOPCAL
0
seal bit; remain in CALMM mode
apply programming voltage at pins T6 and
V
LCDIN
according to Section 18.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Repeat steps 6 to 20 for each bit that should be programmed to 1
21
apply external reset