參數(shù)資料
型號(hào): OM6206Z
廠商: NXP Semiconductors N.V.
英文描述: 65 X 102 pixels matrix LCD driver
中文描述: 65 × 102像素矩陣LCD驅(qū)動(dòng)器
文件頁數(shù): 20/36頁
文件大?。?/td> 195K
代理商: OM6206Z
2001 Nov 14
20
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
OM6206
Notes
1.
2.
3.
4.
5.
The maximum possible V
LCD
voltage that may be generated is dependent on voltage, temperature and (display) load.
Internal clock.
During Power-down mode, all static currents are switched off.
If external V
LCD
, the display load current is not transmitted to I
DD
.
Tolerance depends on the temperature; typical null at T
amb
= 27
°
C; maximum tolerance values are measured at the
temperate range limit; maximum tolerance is proportional to V
LCD
.
For TC1 to TC3.
V
DD
= 2.8 V; no serial clock; T
amb
=
20 to +70
°
C; display load = 10
μ
A.
6.
7.
12 AC CHARACTERISTICS
V
DD
= 2.5 to 5.5 V; V
SS
= 0 V; V
LCD
= 4.5 to 9.0 V; T
amb
=
40 to +85
°
C; unless otherwise specified.
Notes
1.
TC1
V
LCD
temperature
coefficient 1
V
LCD
temperature
coefficient 2
V
LCD
temperature
coefficient 3
note 7
0.76
×
10
3
V
LCD
V/
°
C
TC2
note 7
1.05
×
10
3
V
LCD
V/
°
C
TC3
note 7
2.10
×
10
3
V
LCD
V/
°
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
osc
f
ext
f
frame
t
VHRL
t
RW
Serial bus timing characteristics;
see Fig.15
oscillator frequency
external clock frequency
frame frequency
V
DD
HIGH to RES LOW time
RES LOW pulse width
V
DD
= 2.8 V; T
amb
=
20 to +70
°
C 22
38
38
73
67
67
1
kHz
kHz
Hz
μ
s
ns
20
0
(2)
100
f
osc
or f
ext
= 38 kHz; note 1
see Fig.16
see Fig.16
f
SCLK
t
CYC
t
PWH1
t
PWL1
t
S2
t
H2
t
PWH2
t
H5
t
S3
t
H3
t
S4
t
H4
clock frequency
SCLK clock cycle time
SCLK pulse width HIGH
SCLK pulse width LOW
SCE setup time
SCE hold time
SCE HIGH time
SCE start hold time
D/C setup time
D/C hold time
SDIN setup time
SDIN hold time
V
DD
= 3.0 V
±
10%; note 3
0
250
100
100
60
100
100
100
100
100
100
100
4
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
note 4
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
frame
f
520
---------
=
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