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參數(shù)資料
| 型號： | OM5284EP02 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CMOS single-chip 8-bit microcontrollers |
| 中文描述： | CMOS單芯片8位微控制器 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 106K |
| 代理商： | OM5284EP02 |
Philips Semiconductors
Preliminary specification
OM5234/OM5284
CMOS single-chip 8-bit microcontrollers
1996 Nov 01
5
DC ELECTRICAL CHARACTERISTICS
V
SS
= 0V, V
DD
= 5V
±
10%, T
amb
= 0
°
C to +70
°
C
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
IL
V
IL1
V
IL2
V
IH
V
IH1
V
OL
V
OL1
V
OL2
V
OH
I
IL
I
TL
I
L1
I
DD
Input low voltage, except EA, P1.6, P1.7
–0.5
0.2V
DD
–0.1
0.2V
DD
–0.3
0.3V
DD
V
DD
+0.5
V
DD
+0.5
0.45
V
Input low voltage to EA
–0.5
V
Input low voltage to P1.6, P1.7
–0.5
V
Input high voltage, except XTAL1, RST, P1.6, P1.7
0.2V
DD
+0.9
0.7V
DD
V
Input high voltage, XTAL1, RST
V
Output low voltage, ports 1, 2, 3, except P1.6, P1.7
I
OL
= 1.6mA
6, 7
I
OL
= 3.2mA
6, 7
I
OL
= 3.0mA
I
OH
= –25
μ
A
V
IN
= 0.45V
See note 5
V
Output low voltage, port 0, ALE, PSEN
0.45
V
Output low voltage, P1.6, P1.7
Output high voltage, ports 1, 2, 3, ALE, PSEN
8
0.4
V
0.75V
DD
V
Logical 0 input current, ports 1, 2, 3, except P1.6, P1.7
–50
μ
A
μ
A
μ
A
Logical 1-to-0 transition current, ports 1, 2, 3, except P1.6, P1.7
–650
Input leakage current, port 0, EA, P1.6, P1.7
0.45V < V
I
< 4.7V
±
10
Power supply current:
Active mode @ 16MHz
1, 9
Idle mode @ 16MHz
2, 9
Power down mode
3, 4
V
DD
=5.5V
32.0
6
50
mA
mA
μ
A
k
R
RST
C
IO
Internal reset pull-down resistor
40
225
Pin capacitance
15
pF
NOTES:
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 5ns;
V
IL
= V
SS
+ 0.5V; V
IH
= V
DD
–0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = V
DD
.
2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 5ns; V
IL
= V
SS
+ 0.5V;
V
IH
= V
DD
–0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V
DD
; EA = RST = V
SS
.
3. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V
DD
;
EA = RST = V
SS
.
4. 2V
≤
V
≤
V
max.
5. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
is approximately 2V.
6. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
7. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows: Maximum I
OL
= 10mA per port pin; Maximum
I
OL
= 26mA total for Port 0; Maximum I
OL
= 15mA total for Ports 1, 2, and 3; Maximum I
OL
= 71mA total for all output pins. If I
OL
exceeds the
test conditions, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
8. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9V
DD
specification when the
address bits are stabilizing.
9. I
DDMAX
for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. I
DDMAX
is given in mA.
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