參數(shù)資料
型號(hào)： OL2300NHN
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Fractional-N PLL based transmitter
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC16
封裝： 3 X 3 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT758-1, VQFN-16
文件頁數(shù)： 19/46頁
文件大?。?/td> 951K
代理商： OL2300NHN
OL2300
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2010
19 of 46
NXP Semiconductors
OL2300
Fractional-N PLL based transmitter
Table 24.
Bit 7
PD
[1]
All bits R/W.
Setting the bit XOSL enables the XTAL clock divider that lowers the reference clock
frequency of the PLL by a factor of 2. This allows for example the use of an 18 MHz
crystal for the 315 MHz ISM band.
If the 868 MHz band or the 915 MHz band is selected, bit FBSL must be set to 1. In this
case the power amplifier is driven by the VCO frequency. In other cases bit FBSL has to
be cleared and the PA is driven by the VCO frequency divided by 2.
Table 25.
f
xtal
(MHz)
13.08
13.08
13.08
13.08
[1]
Not a valid ISM band.
6.6.4
FSK mode selection
In order to achieve a narrower signal bandwidth of the FSK spectrum a GFSK-like
modulation, referred to as a Soft-FSK scheme is implemented. The Soft-FSK shape is
modelled by a linear interpolation approach.
The FSK frequency shifting is done in a linear way between (f
RF
f
DEV
) and (f
RF
+ f
DEV
).
Table 26.
Bit 7
The clock frequency of f
ref
is changed by a configurable number of steps which are stored
in the register MRCON (modulation ramp control). Setting the register MRCON to 00h
results in normal FSK operation.
The Soft-FSK ramp time is calculated by:
(7)
Example:
f
ref
= 13.08 MHz, FCON = 0Fh
f
DEV
=
±
11,975 kHz.
For MRCON = 2Ah the frequency step width will result in:
f
step
= 2
×
11975 / 42 = 570.24 Hz.
Address 0Eh; TXCON, transmitter control register
[1]
Bit 6
Bit 5
PDCK
XOSL
Bit 4
FBSL
Bit 3
PAM1
Bit 2
PAM0
Bit 1
ENXR
Bit 0
PLLEN
Oscillator and feedback divider settings
XOSL
0
0
1
1
FBSL
0
1
0
1
f
PLL
(MHz)
868
868
434
434
f
RF
(MHz)
434
868
217
[1]
434
Address 0Dh; MRCON, modulation ramp control
Bit 6
Bit 5
RMP6
RMP5
R/W
R/W
Bit 4
RMP4
R/W
Bit 3
RMP3
R/W
Bit 2
RMP2
R/W
Bit 1
RMP1
R/W
Bit 0
RMP0
R/W
X
-
t
SFSK
2
FBSL
–
(
)
2
-------------------------------------------------
FSK
×
RMP
×
f
ref
=
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