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參數(shù)資料
| 型號： | NZ48F4L0BTZ |
| 廠商： | Intel Corp. |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 無線的StrataFlash存儲器 |
| 文件頁數(shù)： | 88/106頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | NZ48F4L0BTZ |
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Intel StrataFlash Wireless Memory (L18)
April 2005
88
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
Figure 42.
Buffered EFP Flowchart
Write Data @ 1
ST
Word Address
Last
Data
Write 0xFFFF,
Address Not within
Current Block
Program
Done
Read Status Reg.
Y
No (SR[7]=0)
Full Status Check
Procedure
Program
Complete
Read Status Reg.
BEFP
Exited
Yes (SR[7]=1)
Start
Write 0x80 @
1
ST
Word Address
V
applied,
Block unlocked
Write 0xD0 @
1
ST
WordAddress
BEFP Setup
Done
Read Status Reg.
Exit
N
Program & Verify Phase
Exit Phase
Setup Phase
BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE
X = 32
Initialize Count:
X = 0
Increment Count:
X = X+1
Y
NOTES:
1. First-word address to be programmed within the target blockmust be aligned on a write-buffer boundary.
2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address;
WSM internally increments addressing.
N
Check V
, Lock
Errors (SR[3,1])
Yes (SR[7]=0)
Comments
Bus
State
Operation
BEFP setup delay
DReady
Read Status Reg.
No (SR[0]=1)
Repeat for subsequent blocks;
After BEFP exit, a full Status Register check can
determine if any program error occurred;
See full Status Register check procedure in the
Word Program flowchart.
Write 0xFF to enter Read Array state.
Check SR[7]:
0 = Exit Not Completed
1 = Exit Completed
CStatus
Read
Status
Data = Status Reg. Data
BEFP Exit
Standby
If SR[7] is set, check:
SR[3] set = V
Error
SR[1] set = Locked Block
Error
Condition
Check
Standby
Check SR[7]:
0 = BEFP Ready
BEFP
Setup
Standby
Data = Status Reg. Data
ST
Word Addr
Status
Read
Data = 0xD0 @
1
Address
ST
Word
BEFP
Confirm
Write
ST
Word
Data = 0x80 @ 1
BEFP
(Write
V
PPH
applied to VPP
Block
Write
BEFP Setup
Bus
State
Comments
Operation
No (SR[0]=1)
Yes (SR[0]=0)
No (SR[7]=1)
Yes (SR[0]=0)
BEFP Program & Verify
Comments
Bus State Operation
Write
(Note 2)
Load
Buffer
Standby
InCount
Standby
Initialize
Count
Data = Data to Program
Address = 1
ST
Word Addr.
X = X+1
X = 0
Standby
Buffer
Full
X = 32
Yes = Read SR[0]
Read
Standby
Status
DReady
Data = Status Register Data
ST
Word Addr.
Check SR[0]:
0 = Ready for Data
1 = Not Ready for Data
Read
Standby
Standby
Write
Status
Register
Program
Done
Last
Data
Exit Prog &
Verify Phase
Data = Status Reg. data
Address = 1
ST
Word Addr.
Check SR[0]:
0 = Program Done
1 = Program in Progress
No = Fill buffer again
Yes = Exit
Data = 0xFFFF @ address not in
current block
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相關(guān)代理商/技術(shù)參數(shù) |
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| NZ48F4L0QBY | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| NZ48F4L0QBZ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| NZ48F4L0QTY | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| NZ48F4L0QTZ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
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