參數(shù)資料
型號(hào): NTE6508
廠商: NTE Electronics, Inc.
英文描述: Integrated Circuit CMOS, 1K Static RAM (SRAM)
中文描述: 集成電路的CMOS,每1000靜態(tài)RAM(SRAM)
文件頁(yè)數(shù): 3/4頁(yè)
文件大?。?/td> 37K
代理商: NTE6508
Read Cycle Truth Table:
Inputs
Outputs
Q
Z
Z
X
V
V
Z
Z
Time Reference
1
0
1
2
3
4
5
E
H
W
X
H
H
H
H
X
H
A
X
V
X
X
X
X
V
D
X
X
X
X
X
X
X
Function
Memory Disabled
Cycle Begins, Addresses are Latched
Output Enables
Output Valid
Read Accomplished
Prepare for Next Cycle (Same as
1)
Cycle Ends, Next Cycle Begins (Same as 0)
L
L
H
In the NTE6508 Read Cycle, the address information is latched into the on chip registers on the falling
edge of E (T = 0). Minimum address setup and hold time requirements must be met. After the required
hold time, the addresses may change state without affecting device operation. During time (T = 1)
the data output becomes enabled; however, the data is not valid until during time (T = 2). W must
remain high for the read cycle. After the output data has been read, E may return high (T = 3). This
will disable the chip and force the output buffer to a high impedance state. After the required E high
time (TEHEL) the RAM is ready for the next memory cycle (T = 4).
Write Cycle Truth Table:
Inputs
Outputs
Q
Z
Z
Z
Z
Z
Z
Z
Time Reference
1
0
1
2
3
4
5
E
H
W
X
X
A
X
V
X
X
X
X
V
D
X
X
X
V
X
X
X
Function
Memory Disabled
Cycle Begins, Addresses are Latched
Write Period Begins
Data is Written
Write Completed
Prepare for Next Cycle (Same as
1)
Cycle Ends, Next Cycle Begins (Same as 0)
L
L
H
X
X
H
The write cycle is initiated by the falling edge of E which latches the address information into the on
chip registers. The write portion of the cycle is defined as both E and W being low simultaneously.
W may go low anytime during the cycle provided that the write enable pulse setup time (TWLEH) is
met. The write portion of the cycle is terminated by the first rising edge of either E or W. Data setup
and hold times must be referenced to the terminating signal.
If a series of consecutive write cycles are to be performed, the W line may remain low until all desired
locations have been written. When this method is used, data setup and hold times must be referenced
to the rising edge of E. By positioning the W pulse at different times within the E low time (TELEH),
various types of write cycles may be performed.
If the E low time (TELEH) is greater than the W pulse (TWLWH) plus an output enable time (TELQX),
a combination read write cycle is executed. Data may be modified an indefinite number of times dur-
ing any write cycle (TELEH). The data input and data output pins may be tied together for use with
a common I/O data bus structure. When using the RAM in this method allow a minimum of one output
disable time (TWLQZ) after W goes low before applying input data to the bus. This will insure that
the output buffers are not active.
相關(guān)PDF資料
PDF描述
NTE65101 Integrated Circuit 256 x 4-Bit Static Random Access Memory (SRAM)
NTE65 Silicon NPN Transistor High Voltage, Low Noise for CATV, MATV
NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
NTE66 MOSFET N-Ch, Enhancement Mode High Speed Switch
NTE67 MOSFET N-Ch, Enhancement Mode High Speed Switch
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NTE65101 制造商:NTE Electronics 功能描述:IC - NMOS 1K SRAM 450NS 22 LEAD DIP 制造商:NTE Electronics 功能描述:IC-CMOS 1K SRAM 制造商:NTE Electronics 功能描述:IC, SRAM, 1KBIT, SERIAL, 450NS, 22-DIP; Memory Size:1Kbit; Memory Configuration:256 x 4; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Memory Case Style:DIP; No. of Pins:22; Access Time:450ns; Operating Temperature Min:-40C 制造商:NTE Electronics 功能描述:SRAM Chip Async Single 5V 1K-Bit 256 x 4-Bit 450ns 22-Pin PDIP
NTE652 制造商:NTE Electronics 功能描述:CRYSTAL - 4.000 MHZ
NTE653 制造商:NTE Electronics 功能描述:CRYSTAL-5.000 MHZ
NTE6532 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC
NTE654 制造商:NTE Electronics 功能描述:Crystal 10.245MHz 32pF 2-Pin