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參數(shù)資料
| 型號(hào)： | NT7702H-BDT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 240 Output LCD Segment/Common Driver |
| 中文描述： | LCD段輸出240 /通用驅(qū)動(dòng)程序 |
| 文件頁數(shù)： | 7/38頁 |
| 文件大?。?/td> | 384K |
| 代理商： | NT7702H-BDT |
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NT7702
7
Pad Description
Segment mode
Symbol
Function
V
DD
Logic system power supply pin connects to +2.5 to +5.5V
V
SS
Ground pin connects to 0V
V
OR
, V
OL
V
12R
, V
12L
V
43R
, V
43L
V
5R
, V
5L
Power supply pin for LCD driver voltage bias
"
Normally, the bias voltage used is set by a resistor divider
"
Ensure that the voltages are set such that V
SS
≤
V
5
< V
43
< V
12
< V
0
"
To further reduce the differences between the output waveforms of
the LCD driver output pins Y
1
and
Y
240,
externally connect V
iR
and V
iL
(I = 0, 12, 43, 5)
D
0 -
D
7
Input pin for display data
"
In 4-bit parallel input mode, input data into the 4 pins D
0
-
D
3
. Connect D
4
- D
7
to V
SS
or V
DD
"
In 8-bit parallel input mode, input data into the 8 pins D
0
- D
XCK
Clock input pin for taking display data
"
Data is read on the falling edge of the clock pulse
LP
Latch pulse input pin for display data
"
Data is latched on the falling edge of the clock pulse
L/R
Direction selection pin for reading display data
"
When set to V
SS
level "L", data is read sequentially from Y240 to Y1
"
When set to V
DD
level "H", data is read sequentially from Y1 to Y240
DISPOFF
Control input pin for output deselect level
"
The input signal is level-shifted from logic voltage level to LCD driver voltage level, and controls LCD
driver circuit.
"
When set to V
SS
level “L”, the LCD driver output pins (Y1-Y240) are set to level V
5
"
While DISPOFF set to “L”, the contents of the line latch are reset, but read the display data in the data
latch are read regardless of the condition of DISPOFF. When the DISPOFF function is canceled, the
driver outputs deselect level (V
12
or V
43
), then outputs the contents of the date latch onto the next falling
edge of the LP. That time, if DISPOFF removal time can not keep regulation what is shown AC
characteristics, can not output the reading data correctly
FR
AC signal input for LCD driving waveform
"
The input signal is level-shifted from the logic voltage level to the driver voltage level and controls the LCD
driver circuit.
"
Normally inputs a frame inversion signal
The LCD driver output pin’s output voltage level can be set to the line latch output signal and the FR signal
MD
Mode selection pin
"
When set to V
SS
level “L”, 8-bit
parallel input mode is set
"
When set to V
DD
level “H",
4-bit
parallel input mode is set
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT7702H-TABF4 | 240 Output LCD Segment/Common Driver |
| NT7703 | 160 Output LCD Segment/Common Driver |
| NT7703H-BDT | 160 Output LCD Segment/Common Driver |
| NT7703H-TAB18 | 160 Output LCD Segment/Common Driver |
| NT7704 | 240 Output LCD Segment/Common Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT7702H-TABF4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:240 Output LCD Segment/Common Driver |
| NT7703 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:160 Output LCD Segment/Common Driver |
| NT7703H-BDT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:160 Output LCD Segment/Common Driver |
| NT7703H-TAB18 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:160 Output LCD Segment/Common Driver |
| NT7704 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:240 Output LCD Segment/Common Driver |
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