
NT7703
160 Output LCD Segment/Common Driver
1
V1.0
Features
(Segment mode)
!
Shift Clock frequency:
14 MHz (Max.) (V
DD
= 5V
±
10%)
8 MHz (Max.) (V
DD
= 2.5V - 4.5V)
!
Adopts a data bus system
!
4-bit / 8-bit parallel input modes are selectable with a
mode (MD) pin
!
Automatic transfer function with an enable signal
!
Automatic counting function when in “chip select” mode,
which causes the internal clock to be stopped by
automatically counting 160 bits of input data
(Common mode)
!
Shift clock frequency:
4.0MHz (Max.)
!
Built-in 160-bits bidirectional shift register (divisible into
80-bits x 2)
!
Available in a single mode (160-bits shift register) or in a
dual mode (80-bits shift register x 2)
1. Y1
→
Y160
2. Y160
→
Y1
3. Y1
→
Y80, Y81
→
Y160
4. Y160
→
Y81, Y80
→
Y1
The above 4 shift directions are pin-selectable
(Both segment mode and common mode)
!
Supply voltage for LCD drive: 15.0 to 30.0V
!
Number of LCD driver outputs: 160
!
Low output impedance
!
Low power consumption
!
Supply voltage for the logic system: +2.5 to +5.5V
!
COMS process
!
Package: Gold bump die / 186 Pin TCP (Tape Carrier
Package)
!
Not designed or rated as radiation hardened
Single mode
Single mode
Dual mode
Dual mode
General Description
The NT7703 is a 160-bit output segment/common driver LSI
suitable for driving the large scale dot matrix LCD panels
used by PDA's, personal computers and work stations for
example. Through the use of COG technology, it is ideal for
substantially decreasing the size of the frame section of the
LCD module. The NT7703 is good as both a segment driver
and a common driver, and a low power consuming, high-
precision LCD panel display can be assembled using the
NT7703. In the segment mode, the data input is selected as
4bit parallel input mode or as 8bit parallel input mode by a
mode (MD) pin. In common mode, the data input/output pins
are bi-directional and the four data shift directions are pin-
selectable.
Pin Configuration
NT7703
1
V
0
L
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
V
1
2
L
V
4
3
L
V
S
S
/
V
5
L
L
/
R
V
D
D
S
/
C
E
I
O
2
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
X
C
K
L
P
E
I
O
1
F
R
M
D
V
4
3
R
V
1
2
R
V
0
R
D
I
S
P
O
F
F
27
D
U
M
M
Y
D
U
M
M
Y
D
U
M
M
Y
D
U
M
M
Y
105
Y
8
3
Y
8
2
Y
8
1
Y
8
0
Y
7
9
Y
7
8
106
107
108
109
104
28
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
29
30
31
32
185
Y
1
5
5
Y
1
5
6
Y
1
5
7
Y
1
5
8
Y
1
5
9
Y
1
6
0
184 183 182 181
186
D
U
M
M
Y
D
U
M
M
Y
D
U
M
M
Y
D
U
M
M
Y
V
S
S
/
V
5
R