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參數(shù)資料
| 型號： | NT7701H-TABF3 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 160 Output LCD Segment/Common Driver |
| 中文描述： | LCD段輸出160 /通用驅動程序 |
| 文件頁數(shù)： | 8/37頁 |
| 文件大?。?/td> | 466K |
| 代理商： | NT7701H-TABF3 |
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NT7701
8
Segment mode continued
Symbol
Function
S/C
Segment mode/common mode selection pin
#
When set to V
DD
level "H", segment mode is set.
#
When set to V
SS
level "L", common mode is set.
EIO
1
, EIO
2
Input/output pin for chip selection
#
When L/R input is at V
SS
level “L”, EIO
1
is set for output, and EIO
2
is set for input.
#
When L/R input is at V
DD
level “H”, EIO
1
is set for input, and EIO
2
is set for output.
#
During output, it is set to “H” while LP* XCK is “H” and after 160-bits of data have been read, it is set to
“L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H”
#
During input, after the LP signal is input, the chip is selected while EI is set to “L”. After 160-bits of
data have been read, the chip is deselected
Y
1
-
Y
160
LCD driver output pins
These corresponding directly to each bit of the data latch, one level (V
0
, V
12
, V
43
, or V
5
) is selected and
output
Common mode
Symbol
Function
V
DD
Logic system power supply pin connects to +2.5 to +5.5V
V
SS
Ground pin connects to 0V
V
0R
, V
0L
V
12R
, V
12L
V
43R
, V
43L
V
5R
, V
5L
Power supply pin for LCD driver voltage bias.
#
Normally, the bias voltage used is set by a resistor divider
#
Ensure that the voltages are set such that V
SS
≤
V
5
<V
43
< V
12
< V
0
#
To further reduce the differences between the output waveforms of the LCD driver output pins Y
1
and
Y
160,
externally connect V
iR
and V
iL
(I = 0, 12, 43)
EIO
1
Bi-directional shift register shift data input/output pin
#
Is an Output pin when L/R is at V
SS
level “L” and an input pin when L/R is at V
DD
level “H”
#
When EIO
1
is used as an input pin, it will be pulled-down
#
When EIO
1
is used as an output pin, it won’t be pulled-down
EIO
2
Bi-directional shift register shift data input/output pin
#
Is an Input pin when L/R is at V
SS
level “L” and an output pin when L/R is at V
DD
level “H”
#
When EIO
2
is used as an input pin, it will be pulled-down
#
When EIO
2
is used as an output pin, it won’t be pulled-down
LP
Bi-directional shift register shift clock pulse input pin
#
Data is shifted on the falling edge of the clock pulse
L/R
Bi-directional shift register shift direction selection pin
#
Data is shifted from Y
160
to Y
1
when it is set to V
SS
level “L”, and data is shifted from Y
1
to Y
160
when it is
set to V
DD
level “H”
相關PDF資料 |
PDF描述 |
|---|---|
| NT7702 | 240 Output LCD Segment/Common Driver |
| NT7702H-BDT | 240 Output LCD Segment/Common Driver |
| NT7702H-TABF4 | 240 Output LCD Segment/Common Driver |
| NT7703 | 160 Output LCD Segment/Common Driver |
| NT7703H-BDT | 160 Output LCD Segment/Common Driver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| NT7702 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:240 Output LCD Segment/Common Driver |
| NT7702H-BDT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:240 Output LCD Segment/Common Driver |
| NT7702H-TABF4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:240 Output LCD Segment/Common Driver |
| NT7703 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:160 Output LCD Segment/Common Driver |
| NT7703H-BDT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:160 Output LCD Segment/Common Driver |
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