參數(shù)資料
型號(hào)： NT7501
廠商： Electronic Theatre Controls, Inc.
英文描述： 33 X 100 RAM-Map LCD Controller/Driver
中文描述： 33 × 100 RAM的地圖LCD控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù)： 8/38頁(yè)
文件大?。?/td> 319K
代理商： NT7501
NT7501
8
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CS2
SI
SCL
A0
1
CS
Figure 1.
Chip Select Inputs
The NT7501 has two chip select pads,
When these pads are set to any other combination, D0 to D7 are high impedance and A0, E and
When the serial input interface is selected. the shift register and counter are reset.
1
CS and CS2 can interface to a microprocessor when
1
R
CS is low and CS2 is high.
W
inputs are disabled.
Access to Display Data RAM and Internal Registers
The NT7501 can perform a series of pipeline processes between the LSI’s using the bus holder of the internal data bus in order
to match the operating frequency of the display RAM and the internal registers with that of the microprocessor. For example, the
microprocessor reads data from the display RAM in the first read (dummy) cycle, stores it in the bus holder and outputs it onto
the system bus in the next data read cycle.
Also, the microprocessor temporarily stores display data in the bus holder, and stores it in the display RAM until the next data
write cycle starts.
When viewed from the microprocessor, the NT7501 access speed greatly depends on the cycle time rather than the access
time to the display RAM (t
ACC
). It shows the data transfer speed to/from the microprocessor can increase. If the cycle time is
inappropriate, the microprocessor can insert the NOP instruction that is equivalent to the wait cycle setup. However, there is a
restriction in the display RAM read sequence. When an address is set, the specified address data is NOT output at the read
instruction immediately following. Instead, the address data is output only during second data read. A single dummy read must
be inserted after the address setup and after write cycle (refer to Figure2).
N
n
n+1
n+2
DATA
BUS holder
MPU
Internal
timing
Incremented
n
n+1
N
N+1
N+2
Preset
N
Set address n
Dummy read
Data Read address n
Data Read address n+1
N
Address preset
Read signal
Column address
R/W
E
A0
Figure 2.
相關(guān)PDF資料
PDF描述
NT7501H-BDT 33 X 100 RAM-Map LCD Controller/Driver
NT7502 65 X 132 RAM-Map LCD Controller / Driver
NT7502H-BDT 65 X 132 RAM-Map LCD Controller / Driver
NT7502H-TABF1 65 X 132 RAM-Map LCD Controller / Driver
NT7603 2 x 110 W class-D power amplifer, SOT566-3 (HSOP24), Reel Pack, SMD, 13"
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NT7501H-BDT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:33 X 100 RAM-Map LCD Controller/Driver
NT7502 制造商:未知廠家 制造商全稱:未知廠家 功能描述:65 X 132 RAM-Map LCD Controller / Driver
NT7502H-BDT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:65 X 132 RAM-Map LCD Controller / Driver
NT7502H-TABF1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:65 X 132 RAM-Map LCD Controller / Driver
NT75-1 制造商:DBLECTRO 制造商全稱:DB Lectro Inc 功能描述:Low coil consumption. / Switching capacity up to 16A.
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