參數(shù)資料
型號(hào)： NT6861
廠商： Electronic Theatre Controls, Inc.
英文描述： 8-Bit Microcontroller for Monitor
中文描述： 8位微控制器的監(jiān)控
文件頁(yè)數(shù)： 33/44頁(yè)
文件大?。?/td> 455K
代理商： NT6861
NT6861
33
Start condition: When SCL & SDA lines are in HIGH state,
an external device (master) may initiate communication by
sending a START signal (defined as SDA from high to low
transition while SCL is in high state). When there is a
START condition, NT6861 will set the 'START' bit to '1'
and user can poll this status bit to control DDC2B
transmission at any time. This bit will keep '1' until user
clears it. After sending a START signal for DDC2B
communication, an external device can repeatedly send
start conditions without sending a STOP signal to
terminate this communication. This is used by the external
device to communicate with another slave or with the same
slave in different mode (READ or WRITE mode) without
releasing the bus.
Address matched and INTA: After the START condition, a
slave address is sent by external device. When I
2
C bus
interface changes to DDC2B mode, NT6861 will first act
as a receiver to receive this one byte data. This address
data is 7 bits long followed by the eighth bit that indicates
the data transfer direction (R/W ). When NT6861 system
receives address data from external device, it will store if in
IIDAT register. System support 'A0' address by default
and another one set of DDC2 address for user. When user
enable DDC2 function, the system will compare address
data getting from external device with the default address
'A0' and data in the $0013 II_ADR control register written
by user. Either of these address matched, the system will
generate an INTA interrupt flag and this DDC2
communication will be continued. If user sets IEINTA bit to
'1' in advanced and address data matched, the NT6861
system will generate a INTA interrupt. Under the address
matching
condition,
the
acknowledgment to external device. If address data not
matched, the NT6861 will not generate INTA interrupt and
not care the data change on SDA line in the future.
NT6861
will
send
an
Data Transmission direction: At INTA interrupt servicing
routine, user must check the LSB of address data in IIDAT
register. According to I
2
C bus protocol, this bit indicates the
DDC2B data transfer direction in later transmission - a '1'
indicates a request for 'READ MODE' action (external read
data from system); a '0' indicates a 'WRITE MODE' action
(external write data to system). For READ mode and
WRITE mode timing diagram refer to Figure 24 and 25.
The data transfer can be proceeded byte by byte in a
direction specified by the R/W
bit after a successful slave
address is received. User must set TRX bit in the IISTS
register for NT6861 transmission mode - '1' for READ
mode and '0' for WRITE mode.
Data validity and transfer: The data on the SDA line mu be
stable during the HIGH period of the clock on the SCL line.
The HIGH and LOW state of the SDA line can only change
when the clock signal on the SCL line is LOW. Each byte
data is eight bits long and one clock pulse for one bit of
data transfer. Data is transferred with the most significant
bit (MSB) first. If a receiver (external device or NT6861)
cannot receive another complete byte of data until it has
performed some other function, for example servicing an
internal interrupt, it can hold the clock line SCL LOW to
force the transmitter into a wait state. Data transfer then
continues when the receiver is ready for another byte of
data and release clock line SCL. Each byte data is followed
by an acknowledge bit.
Acknowledge: The acknowledgment will be generated at
ninth clock by whom receive data. In the WRITE mode,
NT6861 system must respond to this acknowledgment.
After receiving one byte data from external device, NT6861
will automatically send an acknowledgment by pulling SDA
line to 'LOW'. In the READ MODE, external device must
respond to this acknowledgment and at every byte data
sent, user can read RXAK bit in IISTS register to check if
external sent a ACK or not.
The INTD interrupt: After NT6861 receive the START
condition, it will generate an INTD interrupt at the falling
edge of the ninth clock. User can control the flow of
DDC2B transmission at this INTD interrupt.
The INTD on the WRITE mode: NT6861 read data from
external device. At INTD interrupt, the SCL will be hold
LOW by NT6861. When getting one byte data from II_DAT
register, user can write '00' into II_DAT register and the
SCL will be released. External device can continue
sending next byte data to NT6861. Refer to Figure 24.
The INTD on the READ mode: External device read data
from NT6861. At INTD interrupt, the SCL will be hold LOW
by NT6861. User can check RXACK bit in the IISTS
register whether external device has sent an ACK or not
after one byte data transfer. If external device has sent an
ACK, the RXACK will be '0' (assume the acknowledgment
is LOW signal). When user puts one new byte data into
II_DAT register, the SCL will be released for generation of
SCL transmission clock. The next byte data will be shifted
out
properly.
Figure 25.
Refer
to
相關(guān)PDF資料
PDF描述
NT6862 8-Bit Microcontroller for Monitor
NT6862U 8-Bit Microcontroller for Monitor
NT6868A Keyboard Controller
NT6868A-0011 Keyboard Controller
NT6868A-10100 Keyboard Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NT6861U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller for Monitor
NT6862 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller for Monitor
NT68625 制造商:NAIS 制造商全稱:Nais(Matsushita Electric Works) 功能描述:
NT6862U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller for Monitor
NT68667 制造商:NAIS 制造商全稱:Nais(Matsushita Electric Works) 功能描述:NOVATEK顯示器驅(qū)動(dòng)芯片
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*