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參數(shù)資料
| 型號： | NT6861 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor |
| 中文描述： | 8位微控制器的監(jiān)控 |
| 文件頁數(shù)： | 20/44頁 |
| 文件大小： | 455K |
| 代理商： | NT6861 |
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NT6861
20
12. H/V sync signals processor
The functions of the sync processor include polarity
detection, Hsync & Vsync signals counting, programmable
sync signals output, free running signal generator and
composite sync separation. The processor properly
handles either composite or separate sync signal inputs as
well as no sync signal input. The input at HSYNCI can be
either a pure horizontal sync signal or a composite sync
signal. For the sync waveform refer to Figures 12 and 13.
The sync processor block diagram is shown in
Figure 17. Both VSYNCI & HSYNCI pins have a Schmitt
Trigger and filtering process to improve noise immunity.
Any pulse that is shorter than 125ns will be regarded as a
glitch and will be ignored.
12.1. V & H Counter Register: VCNTL/H, HCNTL/H
Vsync counter: VCNTL/H, the 12-bit read only register,
contains information of the Vsync frequency. An internal
counter counts the numbers of 8
μ
s pulse between two
Vsync pulses. When the next Vsync signal is recognized,
the counter is stopped and the VCNT register latches the
counter value. The counted data can be converted to the
time duration between two successive Vsync pulses by
8
μ
s. If no Vsync comes, the counter will overflow and set
VCNTOV bit (in HVCON register) to HIGH (see Figure 14).
Once the VCNTOV sets to HIGH, it keeps in HIGH state
unless cleared by CLRVOV bit (in CLRFLG register) to
HIGH. When user clears the CLRVOV bit, the VCNT
counter will be reset to zero and begin to count again.
Hsync counter: HCNTL/H, the other 12-bit read only
register pairs contain the numbers of Hsync pulse between
two Vsync pulses (see Figure 15), and the data can be
read to determine if the frequency is valid and to determine
the VIDEO mode. If the HSEL
bit sets to HIGH, the
internal counter counts the Hsync pulses between two
Vsync pulses. If the HSEL
bit clears to LOW, the internal
counter will be reset and begin counting the Hsync pulses
in each 8.192ms interval (see Figure 16). The counted
value will be latched by the HCNTL/H register pairs which
are updated by every Vsync pulse or 8.192ms interval. If
the counter overflows, the HCNTOV bit (in HVCON
register) will be set to HIGH. Once the HCNTOV sets to
HIGH, it remains in the overflow HIGH state unless cleared
by CLRHOV (in CLRFLG register) to HIGH. When user
clears the CLRHOV bit, the HCNT counter will be reset to
zero.
(a) Positive polarity
(b) Negative polarity
Figure 12. Separate H Sync. Waveform
(a) Positive Polarity
(b) Negative Polarity
Figure 13. Composite H Sync. Waveform
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT6861U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller for Monitor |
| NT6862 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller for Monitor |
| NT68625 | 制造商:NAIS 制造商全稱:Nais(Matsushita Electric Works) 功能描述: |
| NT6862U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller for Monitor |
| NT68667 | 制造商:NAIS 制造商全稱:Nais(Matsushita Electric Works) 功能描述:NOVATEK顯示器驅(qū)動(dòng)芯片 |
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