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參數資料
| 型號： | NT68275 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | IIC Bus Controlled On-Screen Display |
| 中文描述： | IIC總線控制屏幕顯示 |
| 文件頁數： | 24/38頁 |
| 文件大?。?/td> | 1389K |
| 代理商： | NT68275 |
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NT68275
24
IIC Bus Communication:
Figure 6 shows the IIC Bus transmission format.
The master initiates a transmission routine by
generating a START condition, followed by a slave
address byte. Once the address is properly
identified, the slave will respond with an AC-
KNOWLEDGE signal by pulling the SDA line LOW
during the ninth SCL clock. Each data byte which
then follows must be eight bits long, plus the
ACKNOWLEDGE bit, to make up nine bits together.
This ACKNOLEDGE bit is sent by NT68275 at
WRITE mode operation and by master, at READ
mode. In the WRITE mode, appropriate row and
column address information and display data can
be downloaded sequentially from the master in one
of the three transmission formats described in
Figure 6 Access Register Operation. In the READ
mode, the content in some control registers can be
transferred to the master. In the cases of no
ACKNOWLEDGE or completion of data transfer, the
master will generate a STOP condition to terminate
the transmission routine. Note that the OSD_EN bit
must be set after all the display information has
been sent in order to activate the displaying circuitry
of NT68275, so that the received in-formation can
then be displayed.
Write Operation of the Control Registers:
After the proper identification by the receiving
device, a data train of arbitrary length is transmitted
from the master. There are three transmission
formats from (a) to (c) as stated below the Timing
section. The data train in each sequence consists
of row address, column address and data. In
format (a), data must be preceded with the
corresponding row address and column address.
This format is particularly suitable for updating
small amounts of data between different rows.
However, if the current information byte has the
same row address as the one before, format (b) is
recommended. For a full screen pattern change
which requires a massive information update, or
during power up situation, most of the row and
column addresses on either (a) or (b) format will
appear to be redundant. A more efficient data
transmission format (c) should be applied. This
sends the starting row and column addresses
once only, and then treats all subsequent data as
display
information.
The
addresses will be automatically incremented
internally for each display information data from the
starting location.
To differentiate the row and column addresses
when transferring data from master, the MSB (Most
Significant Bit) is set as in TAB 8 Transmission: ‘1’
represent row, while ‘0’ for column address.
Furthermore, to distinguish the column address
between format (a), (b) and (c), the sixth bit of the
column address is set to ‘1’, which represents
format (c), and a ‘0’ for format (a) or (b). There is
some limitation on using mix-formats during a
single transmission. It is permissible to change the
format from (a) to (b), or from (a) to (c), or from (b) to
(a), but not from (c) back to (a) or (b).
row
and
column
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相關代理商/技術參數 |
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| NT68520XF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:XGA,SXGA Flat Panel Monitor Controller |
| NT6861 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller for Monitor |
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