參數(shù)資料
型號(hào)： NT5SV16M16AT-7K
廠商： Electronic Theatre Controls, Inc.
英文描述： 256Mb Synchronous DRAM
中文描述： 256Mb的同步DRAM
文件頁(yè)數(shù)： 3/65頁(yè)
文件大小： 814K
代理商： NT5SV16M16AT-7K
NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
REV 1.0
May, 2001
3
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Pin Description
CK
Clock Input
DQ0-DQ15
Data Input/Output
CKE (CKE0, CKE1)
Clock Enable
DQM, LDQM, UDQM
Data Mask
CS
Chip Select
V
DD
Power (+3.3V)
RAS
Row Address Strobe
V
SS
Ground
CAS
Column Address Strobe
V
DDQ
Power for DQs (+3.3V)
WE
Write Enable
V
SSQ
Ground for DQs
BA1, BA0
Bank Select
NC
No Connection
A0 - A12
Address Inputs
—
—
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK
Input
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE, CKE0,
CKE1
Input
Active Highclock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Active Low
CS enables the command decoder when low and disables the command decoder when high. When
the command decoder is disabled, new commands are ignored but previous operations continue.
RAS, CAS, WE
Input
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
executed by the SDRAM.
BA1, BA0
Input
—
Selects which bank is to be active.
A0 - A12
Input
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sam-
pled at the rising clock edge.
During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9,
CA11), when sampled at the rising clock edge. Assume the x4 organization.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10
is low, then BA0 and BA1 are used to define which bank to precharge.
DQ0 - DQ15
Input-
Output
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQM
LDQM
UDQM
Input
Active High
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In
Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output
enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has
a latency of zero and operates as a word mask by allowing input data to be written if it is low but
blocks the write operation if DQM is high.
V
DD
, V
SS
Supply
—
Power and ground for the input buffers and the core logic.
V
DDQ
V
SSQ
Supply
—
Isolated power supply and ground for the output buffers to provide improved noise immunity.
相關(guān)PDF資料
PDF描述
NT5SV16M16AT-7KL 256Mb Synchronous DRAM
NT5SV16M16AT-8B 256Mb Synchronous DRAM
NT5SV16M16AT-8BL 256Mb Synchronous DRAM
NT5SV32M8AT 256Mb Synchronous DRAM
NT5SV32M8AT-75B 256Mb Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NT5SV16M16AT-7KL 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:256Mb Synchronous DRAM
NT5SV16M16AT-8B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:256Mb Synchronous DRAM
NT5SV16M16AT-8BL 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:256Mb Synchronous DRAM
NT5SV16M4DT 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:64Mb Synchronous DRAM
NT5SV16M4DT-6K 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:64Mb Synchronous DRAM
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