- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363669 > NT5DS64M4AW-75B (Electronic Theatre Controls, Inc.) 256Mb Double Data Rate SDRAM PDF資料下載
參數(shù)資料
| 型號： | NT5DS64M4AW-75B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb Double Data Rate SDRAM |
| 中文描述： | 256MB雙數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 11/78頁 |
| 文件大?。?/td> | 1534K |
| 代理商： | NT5DS64M4AW-75B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
REV 1.1
12/2001
11
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Notes:
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-
ing column address, as shown in
Burst Definition
on page 11.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability
of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.
If a Read command is registered at clock edge n, and the latency is
m
clocks, the data is available nominally coincident with
clock edge
n +
m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Burst Definition
Burst Length
Starting Column Address
Order of Accesses Within a Burst
A2
A1
A0
Type = Sequential
Type = Interleaved
2
0
0-1
0-1
1
1-0
1-0
4
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
8
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT5DS64M4AW-7K | 256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-8B | 256Mb Double Data Rate SDRAM |
| NT5DS32M8AW | 256Mb DDR333/300 SDRAM |
| NT5DS32M8AW-6 | 256Mb DDR333/300 SDRAM |
| NT5DS32M8AW-66 | 256Mb DDR333/300 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5DS64M4AW-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS64M4CS | 制造商:NANOAMP 制造商全稱:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
| NT5DS64M4CS-5T | 制造商:NANOAMP 制造商全稱:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
| NT5DS64M4CS-6K | 制造商:NANOAMP 制造商全稱:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。